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Full text of "TRS-80 Manual: Editor Assembler Series I (1981)(Tandy)"

» 



TRS-SO MODEL I III 




I 





Number 

S6-S011 
S6-SQ13 




TM 




CU5TOM MANUFACTURED IN THE USA FOR RADIO SHACK 



A DIVISION OF TANDY CORP 



TRS-80 Series-/ Tape/Disk Editor! Assembler £ 1981 Tandy Corpo- 
ral ion. All rights reserved. 

Derived from original Tape Editor/Assembler © 1978 Microsoft 
Licensed to Tandy Corporation. 

Series 1 Editor Assembler Manual © 1981 Tandy Corporation. All 
rights reserved. 

Reproduction or use without express written permission from Tandy 
Corporation, of any portion of this manual is prohibited. While rea- 
sonable efforts have been taken in the preparation of this manual to 
assure its accuracy, Tandy Corporation assumes no liability resulting 
from any errors or omissions in this manual, or from the use of the 
information obtained herein. 

Please refer to the Software license on the back of this manual for lim- 
itations on use and reproduction of this Software package. 



CONTENTS 



Table of Contents 



1 . Introduction 1 

What is an Editor/ Assembler? 1 

The Series-I Editor/Assembler 1 

The Scope and Organization of This Manual 3 

Notation Conventions 4 

2. Loading the Editor/Assembler 5 

Tape Systems— Level II and Model III basic 5 

Tape Systems— Level I 5 

Disk Systems 6 

3. Using the Editor 7 

4. Using the Assembler 21 

5. Sample Programming Session 31 

6. The z-80 Instruction Set 45 

7. Appendices 

A. Using the tpsrc Utility (Disk Systems Only) 227 

B. rom and trsdos i/o Subroutines 228 

C. z-8o Status Indicators (Flags) 231 

D. Numerical Listing of z-8o Instruction Set 234 

E. Alphabetical Listing of z-so Instruction Set 240 

F. z-so cpu Register and Architecture 246 

Index 253 



INTRODUCTION 



What Is an Editor/Assembler? 

An editor/assembler is a two-part program that lets you communicate with a 
computer in its low-level, "native" language, rather than in some high level, 
"foreign" language like basic or Fortran. We call this native language 
' ' machine-language .' ' 

Using the editor, you enter the machine-language source code, consisting of a 
convenient set of abbreviations and symbols. The assembler then converts or 
assembles this into object code, which the Computer understands. 

But I thought my TRS-80 spoke BASIC! 

Well, you're right, it does. But only because it contains a built-in basic 
interpreter. This interpreter converts or interprets your basic programs into 
object code, which the computer can understand. 

With a Built-in Interpreter, Who Needs Machine-Language? 

Well, if you — 

° Enjoy learning how things — especially, computers — work; 

• Want to do things faster than basic will allow; 

• Want to make the most efficient use of your Computer's memory; 

• Want to modify the way your computer inputs and outputs data 

— then you need machine-language. (Of course, there are plenty of other 
reasons you may want to use it.) 

The Series-I Editor/ Assembler 

There are two versions of this software package, one for tape and one for disk 

systems. 

Tape Version 

Three cassette tapes are included. One contains edtasm, which is the Editor/ 
Assembler. Level II and Model III basic customers may load and run this tape 
using basics system command. The second tape contains system. This 
program is for Level I customers with a minimum of 16K memory. It is loaded 



SERIES I EDITOR/ASSEMBLER 



with the cload command, and prepares the Level I Computer to load the 
edtasm tape. The third tape contains a sample program for tape systems with at 
least 32K of ram. If you have only 16K, you can still type in and use the sample 
program given in Section 5. 

Disk Version 

Two diskettes are included. There is one in Model I trsdos format and one in 
Model III. 

The disk version software includes three programs: 

• edtasm, the Editor/ Assembler program 

• sample/src, a source listing of all the z-80 instructions 

• tpsrc, a utility to read source tapes written by the tape version of the Editor/ 
Assembler and two write object "system" tapes. 

The Series-I Editor/ Assembler is especially good for beginners of machine 
language programming. Its commands and features are fairly simple, and it does 
not require that you understand advanced programming concepts. On the other 
hand, experienced programmers will find this editor/assembler a workable tool 
for all but the most complex, large-scale applications. 



Features 

Editor Features 

• Automatic line numbering for convenient source-code entry. 

• Line renumbering command with automatic renumbering if necessary. 

• Single-letter commands plus optional parameters. 

• Global search capability for changing your source text. 

• Source text may be saved on tape or disk, depending on your computer 
system. 

• Source files on tape or disk may be loaded or "chained" in memory. 

• Source text may be listed to the printer. 

Assembler Features 

• Controlled by a single-letter command with optional switches. 

• Options include: wait on error, no symbol table, list to printer, and trial 
assembly with no object code output. 

• Supports labels up to six characters long. 

• Eight pseudo-ops. 

• Resides in memory with the Editor, so you can easily go back and forth 
between editing and assembling. 



INTRODUCTION 



Scope and Organization of This Book 

In this manual, we will show you how to use the Editor/Assembler. Along the 
way, we'll cover a few principles of assembly-language programming. We'll 
include a sample program. Even if you don't understand assembly-language 
programming, you should be able to try out this sample program. 

In the next section (Section 2), we'll tell you how to load the Editor/Assembler. 
We'll assume you already know how to start-up your Computer, and to get it to 
the basic ready level (cassette systems) or to the trsdos ready level (disk 
systems). There are separate loading instructions for: 

8 Tape systems — Level I 

• Tape systems — Level II and Model III basic 

• Disk systems — Models I and III trsdos 

In Section 3, we'll show you how to use the editor. This section is organized for 
ease of use the first time through. For quick reference later on, there's an 
alphabetical summary of all editor features at the end of Section 3. 

In Section 4, we describe the assembler. Here we'll simply explain the assembly 
command format and syntax. You'll need this information when you get around 
to writing your own assembly-language programs. 

In Section 5, we present a sample assembly-language program. We go through 
all the procedures, from entering the program to loading and executing the 
assembled version. 

Section 6 is a complete z-80 instruction set — the native language of your trs-80. 

This manual is written for use with Model I or III systems using either tape or 
disk storage. There are a few operational differences, depending on which 
system you have. In these cases, we have written separate instructions for the 
differing systems. Follow those pertaining to your Computer. 

What else do I need? 

To write your own assembly-language programs, you'll need more information 
than is contained in this manual. If you know z-80 or another assembly 
language, this manual will probably be sufficient. But if you've never done any 
assembly-language programming, you'll need to do some further study. 

Radio Shack sells an ideal book for future trs-80 assembly-language 
programmers: trs-80 Assembly Language Programming, by William Barden, Jr. 
Its catalog number is 62-2006. Although it was written specifically for the 
Model I trs-80, most of it applies as well to the Model III. 



SERIES I EDITOR/ASSEMBLER 



Notation and Special Terms Used in This Book 



Notations 

COMPUTER TYPE 

italic type 

CffiB 

[optional 
information] 



Indicates material that is input to or output from the 
Computer. Note: All computer prompts in this manual 
are given in uppercase. 

Represents variable information that you provide in a 
command, (i.e., file names, line numbers, etc.) 

Key which you should press. These will not be visible 
on the screen. 

Square brackets enclose optional parts of a command. 



Special Terms 

source code (or text) An assembly-language source program you have loaded 
from tape or disk or typed. 



source file 
object code 
object file 



An assembly-language source program you have saved 
on tape or disk. 

The output from the assembler, i.e., coded z-80 
instructions. 

Object code stored on tape or disk so that it may be 
loaded and executed. 



LOADING THE EDITOR/ASSEMBLER 



Part Two: 



ig the Editor/Assembler 

Tape Systems — Level II and Model III BASIC 

The Editor/Assembler is a machine-language program stored on tape at 500 
baud. Its file name is edtasm. 

1. Turn on your Computer and press (ENTER) to the prompt for memory size. (In 
Model III systems, first type L to the cass? prompt.) 

2. Get your recorder ready to play the Editor/Assembler tape. 

3. Type SYSTEM (INTER) , then EDTASM (ENTER) . The Computer will begin loading 
from the tape. After a successful load (takes about 2 minutes), the *? prompt 
will reappear. 

4. Type / (ENTER) . The Editor/Assembler starts by displaying a heading followed 
by an asterisk at the beginning of the next line. The asterisk is the prompt, 
telling you the Editor/Assembler is waiting for a command. 

Now skip to Section 3 . 

Tape Systems — Level I BASIC 

Before you can load the Editor/ Assembler tape, you must get your Computer 
into a "system" mode. The system tape does this. 

1 . Turn on your Computer. It should be in the ready mode. 

2. Get your recorder ready to play the system tape. 

3. Type CLOAD (ENTER) . The Computer will begin loading from the tape. After a 
successful load (takes about 2 minutes), a "PRESS ENTER WHEN CASSETTE 
IS READY" will appear on the next display line. Your Computer is now in 
the system mode. 

4. Prepare the recorder to play the edtasm tape. 

5. Press (ENTER) . The Computer will begin loading from the tape. After a 
successful load (takes about 2 minutes), the Editor/ Assembler will start by 
displaying a heading followed by an asterisk at the beginning of the next line. 
The asterisk is the prompt, telling you the Editor/ Assembler is waiting for a 
command. 



SERIES I EDITOR/ASSEMBLER 



6. Volume setting may need to be adjusted for a successful load. 
Now skip to Section 3 . 

Disk Systems 

The program file name for the Editor/Assembler is edtasm/cmd. 



1. Under trsdos ready, type: EDTASM (ENTER) , 

2. The Editor/Assembler will start by displaying a heading, followed by an 
asterisk on the next line. The * is the prompt, indicating the Editor/ 
Assembler is waiting for a command. 



USING THE EDITOR 



Jr&rt lilTGC* 



Using the Editor 



Assuming you have just started the Editor/Assembler, it is displaying an asterisk 
on the screen. This is the "prompt." It tells you the Editor/Assembler is waiting 
for a command. 

The Editor consists of commands that allow you to create, edit, save and load 
your source programs. We'll divide these commands into three groups: 

• Text-handling — creating and modifying the source program. 

• File input/output — saving the program on disk or tape and loading it from disk 
or tape. 

• Miscellaneous — getting the memory status, exiting from the Editor/ 
Assembler. 

Special Terms 

Before using the commands, we need to define a few special terms used in this 
section. 

"text" is the information (source program) that you have entered into the 
Computer. The insert command allows you to begin entering text one line at a 
time, pressing (ENTER) at the end of each line. The Editor automatically numbers 
each line. 

"text buffer" is the area in memory where your text is stored. 

"current line" is the line most recently entered, displayed, or referenced in a 
command. 

"file" is the source text stored on tape or disk. 

"file name" is the name given to the file. In tape systems, the file name consists 
of from one to six letters or numbers. In disk systems, the file name follows the 
rules of trsdos file specifications (for full details, see your trsdos reference 
manual): 

filename [/ext] [.password] [:d] 

"inc" or "increment" refers to the number which is used to compute 
successive line numbers for your text. When you start the Editor, the increment 
equals 10. 



SERIES S EDITOR/ASSEMBLER 



"line ref" or "line reference" is the way you specify a single line in your text. 
A line reference may be any number from to 65529, or any of the following 
special symbols: 

* First line in the text buffer 
, The current line 

* The last line in the text buffer 

"line range" indicates a range of lines in your text file; it is a pair of line 
references separated by a colon . 

line-ref:line-ref 

"tof" and "eof" — refer to top of file (first line) and end of file (end of file). 
The Editor will use these abbreviations in certain messages to you. 

Sample Commands 

These examples are simply to show the use of the special terms and notation. 
The commands are explained later in detail. 
P 100 "Printline 100." 

P # : . "Print text from the first line to the current line. 

D . "Delete the current line." 

I line ref., inc. "Start inserting at line, using inc as an increment between 

lines, ("line ref." and "inc" are variables you replace with 

appropriate values.) 

A Few Words about Spaces 

In general, spaces are not significant inside editor commands. You may use 
them or omit them. Exception: No spaces inside a file name, line reference or in 
the command ©-Find. 

Special Keys 



(ENTER) To complete a command or a line of text, you must press this 

key. 



(BREAK) To cancel a command or to stop inserting text, press this key. 

The line that the (BREAK) is pressed is not saved. Press (BREAK) 
on the line following the last line. 

© Press this key to see the previous line of text. 

© Press this key to see the next line of text. 

© This key erases the previously typed character. 

© This functions as a tab key. You will use it while inserting 

text. The tab positions are spaced eight columns apart. 

left (SHIFT) HO This erases the line you have been typing. 

fJD This causes a pause in a listing or printout. Press any key to 

continue. 

Editor Commands 

We'll cover the commands in a typical sequence in which you might use them. 
For an alphabetical summary, see the end of this section. 



USING THE EDITOR 



Text Handling Commands 

Inserting Your Text 

When the asterisk is displayed, you may type in a command — not your source 
text. To enter source text, you must get into the insertion mode. 



First, to get your Computer "in step" with our examples, type D #:* (ENTER) . 
That erases any text that you might already have entered into the text buffer. 



Now we'll go into the insertion mode. Type I (ENTER). The Computer will 
display 00100. All we do is type in text for line 100 and press (ENTER) . The 
Computer will automatically provide the next line number. 

(30100 5 ANY CHARACTERS FOLLOWING A SEMI-COLON (!) IS A 



COMMENT (ENTER) 
00110 

We may continue like this until we finish entering the text. Remember to press 
(ENTER) at the end of each line. 



00110 5 PRESS -> AT THE START OF THE NEXT L INE (ENTER) 
00120 RET 5 A VERY SHORT PROGRAM (ENTER) 

00130 

In line 120, we pressed tab CD once at the beginning of the line, and once after 
ret. Tabs are very important in source programs; they are used instead of spaces 
to separate the standard fields in an assembly-language program. (We'll explain 
further in part 4.) 



That's all the text we want to type in for now, so press (BREAK) . The asterisk will 
reappear on the next line. 

Displaying Your Text 

To see the text, use the Print command. For example: P #:* (ENTER) . This tells 
the Computer to display all the lines in the text buffer. To see a single line, 
specify that line, as in: P wo (ENTER) . Another way to display lines one at a time 
is with © (previous line) and & (next line). 

If you omit a line reference, the Computer will display a screenful of lines, 
starting at the current line. This is a good way to look at a large text file, one 
screenful at a time. Simply press P (ENTER) to see the next screenful. 

Note: If the total file is to be displayed you may execute T (ENTER) prior to Print 
command to insure that current line is toe 

Getting a Hard-Copy of the Source Program 

To output to a line printer instead of to the display, substitute "h" (hard copy) 
for "p". For example, the command H #:* prints out the entire source program. 
If printer is not ready press (BREAK) to return to command line. 

(For instructions on getting hard copy of an assembled program, see Section 4.) 



SERIES I EDITOR/ASSEMBLER 



Adding Lines between Existing Lines 

Suppose you want to add a line between lines 100 and 110. Use the Insert 
command, but specify a starting line number between 100 and 110: 

I 105 



1105 iTHIS LINE IS ADDED CENTER) 



1115 (BREAK) 



When you pressed (ENTER) for line 105, the Computer used the current increment 
(10) to generate line 115, which will not be between 100 and 110. To insert more 
than one line between any two lines, you can specify an increment of 1. 

For example, 



I 105.1 (ENTER) 
0010B 

Line 105 is already in use, so the Computer gives you the next number, using an 
increment of 1 : 



510B iWE'LL JUST TYPE IN A FEW LINES (ENTER) 

5107 iNOTICE THAT THE INCREMENT OF 1 IS STILL IN USE (ENTER) 



00108 iWHAT WILL HAPPEN WHEN WE REACH LINE 110? (ENTER) 



0010S ;THAT LINE IS ALREADY IN USE . , , (ENTER) 



1110 i. , . BUT EDTASM GIVES YOU THAT NUMBER ANYWAY. (ENTER) 



00111 (BREAK) 

A line "collision" was about to occur when you entered line 110, since that 
number was already in use. So the Editor automatically renumbered all lines. 

To begin inserting lines at the end of the file, use the Bottom command, 
B (ENTER) . This makes the current line the last line. 

Changing a Line in Your Text 

To make a change within a line of text, use the Edit command. This puts you in 
a special intra-line edit mode in which several useful functions are available. To 
begin editing a line, type E followed by the line number (or line symbol "#", 
"*", ".") and press (ENTER) . The Computer will display the line number 
followed by the cursor (blinking block or underline). This is your "working 
copy" of the line. Changes you make will not take effect until you exit from the 
intra-line edit mode. 



To exit from the intra-line edit mode, press (ENTER) or E (ENTER) and changes are 
saved. Press (BREAK) or (ENTER) and the line remains in its original form. 



10 



USING THE EDITOR 



Here are the functions available in the intra-line edit mode: 



(D Lists the line in its current form and starts a new working 

copy on the next line. 

n rSPACEBAR) (Spacebar) Moves the cursor forward n spaces, showing the 

next n characters in the line. If n is omitted, 1 is used. 

QD Moves cursor back one space in the line, but does not erase 

the character from the working copy. 

n © c (Search) Positions the cursor at the /7th occurrence of 

character e, counting from the current cursor position. If n 
is omitted, positions to the first occurrence after the current 
position. 

n d) Deletes the next n characters. If n is omitted, 1 is used. 

n (K) c (Kill) Deletes all characters up to the nth occurrence of 

character e. If n is omitted, deletes up to the first 
occurrence. 

n © cl . . . en Changes the next n characters to characters cl . . . en. 

® (Again) Cancels all changes made and lets you edit the line 

again. 

CD newtext Insert newtext. Insertion will continue until you press 

(SHIFT) & or (ENTER) . While inserting, the CD key will erase 
a character, and the (SPACEBAR) will insert a space. You must 
exit from this insertion function before you can use any of 
the other editing functions. 

(X) (Extend) Begin inserting at the end of the line. 

© (Hack) Delete remainder of the line and begin inserting at 

the current position. 

[ENTER) or (£) Exits to the * command level. The changes you made will 

take effect. 

(BREAK) or @ (Quit) Exits to the * command level. The changes you made 

will be canceled. 

The best way to learn to use these edit functions is to experiment with them. For 
example, type E (EtflfR) to start editing the current line. The Computer will 
display the line number. Press (D to see the line in its current form and start a 
new working copy. Now try each of the commands listed above. 



Remember: To exit from the intra-line editor at any time, press (ENTER). To stop 
the insertion function but continue editing, press (SHIFT) ® . 



11 



SERIES I EDITOR/ASSEMBLER 



Replacing a Line 

You cannot use the Insert command to replace a line, because the Computer will 
always renumber the lines in case of a line collision. To replace a line, type R 
followed by the line reference and press ( ENTER) . 

For example, to replace line 100, type: R 100 ( ENTER) . The Computer will 
display 00100. Go ahead and type in the new text for this line. When you press 
(ENTER) , the Computer will act just as it does in the line insertion mode: it will 
compute a new line number using the current increment and renumbering the 
lines if necessary to avoid a collision. From this point on, you are inserting, not 
replacing. Only line 100 is replaced. 

Deleting Lines 

To delete a range of lines, type D line range. For example, 

D 100 Deletes line 100 

D . Deletes the current line 

D 100:120 Deletes all lines from 100-120 

D * : * Deletes all lines (first to last) 

Finding a String within Your Text 

The Find command searches through your text for any one word string you 
specify, and tells you which lines contain the text. 

Suppose you have a large text file in memory, and you want to change each 
occurrence of "lbl" to "label." The Find command will identify each line 
that contains "lbl." Simply type: T (ENTER) to position the current line to the 
beginning of the text, then type FLBL (ENTER) . The Computer will search for the 
string of characters immediately following the F and ending with the carnage 
return ( (ENTER) ). 

The editor will print the line number of the first occurrence of lbl. That line 
becomes the current line. You may begin editing it by typing E (ENTER) . 

To find subsequent occurrences of lbl, simply type F (ENTER) . The editor 
continues searching at the current position and remembers the string being 
searched. 

Remember: (1) Type in the search string immediately after the "F" with no 
spaces, unless the search string starts with spaces. (2) The Find command 
begins searching at the current line, so set the current line to tof first if you 
want to search through the entire text. 

Renumbering Your Text 

After inserting lines (and having them automatically renumbered), you may 
want to renumber them "manually." The Number command does this. Type N 
start-line, increment (ENTER) . Start-line will be the lowest-numbered line in the 
renumbered program. 



12 



USING THE EDITOR 



For example, the command: N 1000 , 10 CENTER) renumbers the text 1000, 
1010, 1020, etc. 

After renumbering, the current line is the last line in the file, and the increment 
is what you specified in the n command. 

If no start line is typed, the renumbering will begin with the current line. If no 
increment is specified, 10 is used. 

Source File Input/Output Commands 

In this section, we'll show how to save a source program and then reload it. 
(For instructions on outputting and loading an object file, see Section 4.) 

There are three general groups of editor i/o commands: 

• Writing the source program to tape or disk 

• Loading the source program from tape or disk 

' Printing the source program on the display or on a line printer. We've already 
described these commands (h and p). 

Saving the Source Program 

Once you have typed in and edited a source program, you should save it on tape 
or disk. That way, if you ever need to modify the source program, you won't 
have to retype it; you can simply load it and make changes. 

The tape version of Editor/Assembler always assumes you want tape i/o, and the 
disk version assumes you want disk i/o. (Disk systems may load source tapes 
via the tapesrc utility, described later in the appendix.) 

Note to Model III Customers: All tape i/o is done at 500 baud, regardless of the 
cassette baud rate you selected when you started up the Computer. 

Tape Systems 

1 . Using a blank cassette tape, put your recorder into the record mode. 

2. Type tifile (ENTER) . Use a file name from one to six characters. You may omit 
the file name, in which case the tape file will be named noname. 

Example: 



N MOVE (ENTER) 

3. The Editor/Assembler will prompt you to get the cassette recorder ready. Be 
sure it's in the record mode, then press (ENTER). The Editor/Assembler will 
write the text onto the tape. 

4. After writing the tape, the Editor/Assembler will return to the command 
mode (asterisk). 

5. Make at least one additional tape copy of the program. 



13 



SERIES I EDITOR/ASSEMBLER 



6. Remove the tape from the recorder and label it. Be sure to identify it as a 
source tape. 



Disk Systems 



1. Type W file (ENTER) . For file, use a standard trsdos file name with an optional 
password and drive specification. The Editor will automatically add the 
extension /src to the file name. To override this, include a different extension 
in the file specification. 

You may omit the file name, in which case the file will be called noname/ 
src. 

Example: 



W MOVE ( INTER) 

writes the source program into the file move/src. 

2. After writing out the file, the Editor will return to the command mode 
(asterisk). 

Loading a Source Program 

Tape Systems 

1. Prepare the recorder to play the source tape. 



2. Type L file (ENTER) . For file, substitute the correct file name. If there are 
several files on the tape, the Editor will search through them until it reaches 
the one you named. You may omit the file name, in which case the first file 
on the tape will be loaded. 

Before the Editor starts loading from the tape, it will prompt you to get the 
cassette recorder ready. Press (ENTER) when ready. 

3. After loading the source program, the Editor will return to the command 
mode (asterisk). 

Disk Systems 

1 . Type L file (ENTER) . For file, specify the file in standard trsdos form. If the 
specification you give does not include an extension, the Editor will 
automatically use the extension /src. 

You may omit the file specification. The Editor will then attempt to load a file 
named noname/src. 



14 



USING THE EDITOR 



(If you already have a source program in the text buffer, the Editor will 
warn you: 

TEXT IN BUFFER, CHAIN FILES? 

If you want to add the disk file onto the end of the current text in memory, 
type Y (ENTER) . This will chain the new file onto the end of the file in memory 
and automatically renumbers the total file. If you don't want to "chain" the 
files, but wish to erase the current file and load the new one, type N (ENTERj.) 

2. After loading the file, the Editor will return to the command mode (asterisk). 

Miscellaneous Commands 

Determining the Memory Status 

To find out the size of the current source program and the amount of free 
memory, type M (ENTER) . The status will be shown in bytes. 

Exiting from the Editor/Assembler 

The quit command (0 (ENTER) ) takes you out of the Editor/Assembler and back 
to trsdos or basic (if you are in a level II computer). Before using this 
command, be sure to save your source program, if desired, because you won't 
be able to recover it simply by restarting the Editor/Assembler. 



15 



SERIES I EDITOR/ASSEMBLER 



Editor Error and Warning Messages 



BAD PARAMETER(S) 



BUFFER FULL 



LINE NUMBER TOO LARGE 



NO SUCH LINE 



NO TEXT IN BUFFER 



STRING NOT FOUND 



This indicates that you gave the 
editor an invalid command. 
Check the syntax used, and the 
values of parameters given (they 
may be out of range). 

The area assigned to text 
storage is full. You may be able 
to split the source text into two 
modules. 

During the generation of new line 
numbers (insertion or line 
renumbering) a line number 
greater than 65529 was needed. 
This is too large. Use a smaller 
line number increment. 

A reference was made to an 
unused line number. 

All commands except load, 
insert, memory-status, and quit 
require some text to be in the 
buffer. 

You issued a find command and 
the editor could not locate the 
string you specified. Be sure you 
had the current line set properly 
(find begins searching at the 
current line number). 



16 



USING THE EDITOR 



ki$mmsism'£m»Ma*g3smmgmmMMmsmmMmmmiimg. 



Editor/ Assembler Alphabetical Summary 

Special Keys 



(ENTER) 


Executes the current command. 


(BREAK) 


Cancels or interrupts a command. 


33 


Erases the last character typed. 


(♦j 


Displays the previous text line. 


(jST) 


Displays the next text line. 


(SHIFT) (Jj 


Erases the entire line. (Use left 
shift key only) 


CD 


Tabs forward eight spaces. 


G@3 


Pauses execution of a command; 
press again to continue. 


(SHIFT) (*J 


Escapes from the character 
insertion command in the edit 
mode. (Use left shift key only) 



Symbols and Abbreviations 



# 


First line in text 


* 


Last line in text 




Current line in text 


line ref 


A single line number or line symbol 
(#, *, or.). 


line range 


A pair of line refs separated by a 
colon (line ref : line ref) 


inc 


An increment between lines. 



17 



SERIES I EDITOR/ASSEMBLER 



Commands 



A [file] [.switch , 



D [line ref or line range] 

E [line ref] 

Subcommands 

CD 

n (SPACEBAR) 

CD 

n©c 

n(B 

n®c 

n ©c7 . . .en 



CD newtext 

m 
m 

[ENTER] or (El 



(BREAK ) or (Ql 
F [text string] 



H [line range] 

I [line ref] line] 

L [file] 

M 

N [//ne ref] [,inc] 

P [//ne range] 



Assemble. Switches are: lp (line 
printer, we (wait on error), nl (no 
listing), ns (no symbol table), no 
(no object code output). 

List bottom (last) line of text. 

Delete line(s). 

Edit line ref. 

Lists working copy of line 

Advance n spaces. 

Backspace 1 space. 

Search for nth occurrence of c. 

Delete next n characters. 

Kill up to nth occurrence of c. 

Change next n characters to 

d . . .en. 

Cancel changes and start again. 

Insert newtext. Press (ENTER) or 

(SHIFT) W to quit. 

Extend line. 

Hack rest of line and begin 

inserting. 

Exits to the command level; 

changes take effect. 

Cancels changes and quits editing. 

Find the fexf string immediately 
following the letter "f"; or find the 
current text string. (No space 
between CD and text string). 

List lines on the printer. If printer 
not ready use (BREAK) to recover. 

Insert at line ref using inc. If no 
line ref has been determined 100 
is used. 

Load a source file. 

Display memory status. 

Renumber text. 

List lines on the display. 



18 



USING THE EDITOR 






Quit Editor/ Assembler; return to 




trsdos or basic (Level II). 


R [line ref] 


Replace line and continue in the 




line insertion mode. 


T 


List top (first) line of text. 


M [file] 


Write a source file. 



19 



USING THE ASSEMBLER 



Part Four: 



Using the Assembler 



In Section 3, we showed you how to type in, edit, and save a source program. 
For a source program, we used an arbitrarily chosen text. 

Now we are ready to discuss the assembler — the software that converts your 
source text into object code that can be understood by the trs-80*s z-so 
microprocessor, and writes this object code to a tape or disk file. We'll break 
this section up into three parts: 

A. The Assemble command — syntax, options, file output, error conditions, etc. 

B. Assembler language — definitions, syntax, input/output format, etc. 

If you're new to assembly language, you don't have to read all this now. You 
may skip to Section 5, which presents a sample programming session. This will 
give you hands-on experience with the Editor/ Assembler. Then, when you come 
back to this section, you'll have a better idea of what it's all about . . . 



The Assemble Command 

You enter the Assemble command at the command level (asterisk). It consists 
of the abbreviation "a" followed by a space and an optional file name and 
optional switches. (We call them ''switches" because they turn various 
functions on and off.) 

There are various combinations of spaces and commas that will work in the 
assemble command. For simplicity, we'll stick with one workable set of rules 
for command syntax. 

A [file] [, switch . . .] 

The file name and switch are optional. (If no file name is used, you must still 
type in a space after the "a.") Every switch used must be preceded by a 
comma. Spaces before or after the file are acceptable and have no effect. 

A source program must be originated in ram or loaded into ram before it can be 
assembled. 



21 



SERIES I EDITOR/ASSEMBLER 






For example: 



A ZAP,NS,|\IL>HE (INTER] 

"zap" is the file name; "ns", "nl" and "we" are switches. The commas are 
required. The meaning of this and the following commands will be explained in 
the following pages. 



A .N0»WE»NS CENTER) 
No file name is given. 
As another example: 



A (SPACEBAR) (INTER) 

No file name or switches are specified. 

File Name 

The file name you specify will be assigned to the tape or disk object file. If you 
omit a file name, "noname" will be used. (For further details, see File Output 
later in this section.) 

Switches 

If you don't specify any switches in your assemble command, the Assembler 
will do the following: 

• Print the assembly listing on the screen 

• Print error and warning messages in the listing without pausing 
Print a symbol table after the listing is completed 

• Output the object code to tape or disk, using the file name you specified (or 
"noname" if you omitted one) 

Here are the switches available. You may use as many as you want in any order. 
Remember to put a comma before each switch used. 




(Line printer) Output listing, error messages, and 
symbol table to the line printer, not to the display. 

(Wait on error) Pause after each error message; 
operator presses (ENTER) to continue. 

(No listing) Don't output an assembly listing. 

(No symbol table) Don't output a symbol table. 

(No output) Don't output any object code. 



22 



USING THE ASSEMBLER 



File Output — Disk Systems 

If you do not specify the no switch, and if no terminal errors occur during the 
assembly, the Assembler will write the object code to the disk file you specify. 

Use a standard trsdos file name with an optional password and drive 
specification. The Assembler will automatically add the extension "/cmd" to 
the file name. To override this, include a different extension in the file 
specification. 

If you omit a file specification, the Assembler will use "noname/cmd" as the 
object file. 

Examples: 

A ZAP»N0»WE 

Waits on errors, does not output object code. 

A ZAP.LP 

Outputs the assembly listing to the printer, outputs object code to zap/cmd. 

Use of Object Files 

Every object file is stored in a special format that allows it to be loaded and 
executed by trsdos. An object file cannot be loaded by the Editor/Assembler. 
(Since it is no longer in text form, the Editor/ Assembler can't do anything 
with it.) 

To load and execute an object file program while you are in the trsdos ready 
mode, type the file name and press (ENTER) . If the extension is "/cmd," you 
don't need to include it in the file name. 



To load an object file and return to trsdos ready, type LOAD filename (ENTER) . 
In this case, you must include the extension even if it is "/cmd." For further 
details on the use of object files, see Section 5. 

Now skip ahead to "Assembler Error Messages." 

File Output — Tape Systems 

Note to Model III Customers: All tape output is done at 500 baud. 

If you do not specify the "no" switch, and if no terminal errors occur, the 
Assembler will write the object code to cassette tape, using the file name you 
specify. The file name may be from one to six characters long. If you omit one, 
"noname" will be used. 

Before writing the tape, the Assembler will prompt you to get the cassette ready. 
Using a blank tape, prepare the recorder to record; when ready, press (ENTER) . 
The Assembler will then write the tape. 

Make at least two copies of each object file. Remove the cassette and label it as 
an "object" tape. 



23 



SERIES I EDITOR/ASSEMBLER 



Use of Object Tapes 

Object tapes are stored in a special format for loading via the system command. 
(Level I systems must first load the system tape; then the object tape.) An 
object file cannot be loaded by the Editor/ Assembler. (.Since it is no longer in 
text form, the Editor/Assembler can't do anything with it.) 



To load an object tape while in BASIC, type: SYS TEM (ENTER) then filename (ENTER) 
. After the tape has been loaded, you may press (BREAK ) to return to 
basic, or / address (ENTER) to begin execution at the specified address. If you 
type / (ENTER) , omitting the address, an address specified on the tape itself will 
be used. (For details, see the .Section 5.) 



Assembler Error Messages 

Four kinds of errors may occur after you enter an assemble command. 

1. Command errors. If there is an error in your command, no assembly will be 
attempted. The Assembler will display the message "bad parameter(S)" 

2. Terminal errors. During assembly, an unrecoverable error occurred. The 
assembly is cancelled. 

The only terminal error is "symbol table overflow." This occurs when 
there is not enough memory to handle the symbol tables required for 
assembly. Use a machine with more memory (if possible), or break the 
program up into modules and assemble them separately. 

3. Fatal errors. One of the source lines contained an error. No object code is 
generated for the offending line, but the assembly continues. Here are the 
terminal errors: 



BAD LABEL 


Invalid sequence of 




characters were used 




as a label. (See 




"labels.") 


EXPRESSION ERROR 


An invalid expression 




was used as an 




operand. (See 




"expressions.") 


ILLEGAL. ADDRESSING MODE 


One of the operands 




used is illegal with the 




specified Z-80 




instruction. 


ILLEGAL OPCODE 


Unrecognizable 




characters were used 




in the opcode 




(mnemonic) field. 


MISSING INFORMATION 


Mnemonic or 




operands are missing. 



24 



m /ft*. (p%, g=«« m m w*% a 



4. Warnings. A probable error occurred, but the assembler will generate object 
for the offending line anyway. The code may not be what the programmer 
intended. Warning messages are: 



BRANCH OUT OF RANGE 


Relative branch 




instruction outside of 




the range -126 to 




+ 129 bytes. 




Instruction is 




assembled to branch 




to itself. 


FIELD OVERFLOW 


An operand (number 




or expression) is out 




of range for the 




specified instruction. 




The operand is set 




equal to zero. 


MULTIPALLY DEFINED SYMBOL 


A label has been used 




to identify two different 




places or represent 




two different values. 




All but the first 




definition will be 




ignored. 


MULTIPLE DEFINITION 


A duplicate operand is 




used. 


NO END STATEMENT 


No end statement was 




found. 


UNDEFINED SYMBOL 


The operand field 




contains a symbol 




which has not been 




defined. A value of 




is used for this 




symbol. 



Assembly Language 

In the first part of Section 4, we discussed the use of the assemble command. In 
this part, we'll discuss Assembly as a programming language. 

An assembly program is made up of source statements. Each source statement 
consists of up to four fields. A "field" is a range of columns on the display. 
We'll agree to consider column 1 to be the first column of source text. Column 1 



25 



SERIES I EDITOR/ASSEMBLER 

■: '■ .-, ■. ■■■■■■■■. ■■.'.. ■..:'■■.■.. '■'■'■: ■.-■■:..■:"" ■■■■■: 






— ^^— — ^— i 



is the first column after a space that follows the line number. Source statements 
are written using the i (insert) command. 



Field 


Column Range 


Label 


1-6 


Mnemonic 


9-15 


Operand(s) 


17-31 


Comment 


May begin anywhere but must be 




preceeded by a semi-colon (;). 



Labels are used to identify individual source statements. A label may be from 
one to six characters. It must start with an alphabetical character. For example: 

MOVE 
LOOP 
LOO Pi 
CLS 
Ti 

are all valid labels. Labels must start in column 1. 

Mnemonics are the abbreviations used to represent z-so operations, for example: 

LD Load 

DEC Decrement 

RET Return 

Mnemonics are also called "operation codes" or "opcodes." Mnemonics must 
start in column 9. 

Operands are the values used by certain assembler statements. An operand may 
be a z-80 register or i/o port, or a one- or two-byte value. For example: 



LD 



A »3 



tells the z-80 to load into register a the number 3. "a" and "3" are operands. 
Symbols may be used in place of actual numbers. For example: 



LD 



HL .VIDEO 



tells the z-80 to load into register hl the value for video (defined elsewhere in the 
program). The first operand must start in column 17. 

Comments document the program. They are ignored by the assembler. A 
comment may begin in any column of a source statement, subject to the 
following limitations: All comments start with a semi-colon, which tells the 
assembler to ignore the rest of the line. 

When you type in a source program, use a tab (CD key) to separate the fields, 
not spaces. This method is faster and saves memory. Furthermore, the tab 
settings correspond to the first columns in each field. 



26 



USING THE ASSEMBLER 



Example: 

00100 
00110 
00120 
00130 
00140 
00150 
001B0 
00170 
00180 



THIS IB A SAMPLE PROGRAM 



!LABEL 



BEGIN 



MNEM, 

ORG 

LD 

LD 

LD 

RET 

END 



0PERAND(S: 
32700 
HL.3C00H 
A.'*' 
(HL) ,f\ 



COMMENT 

5FOR 1GK MACHINES 

i(HL)= VIDEO RAM) 

i write asterisk to 01 deo 
! return to caller 
;end of source program 



Lines 100-120 are comments. Lines 130-170 consists of assembly-language 
statements followed in most cases by comments. 

There should be one tab character at the end of each field. Spaces (entered via 
(SPACEBAR) should only be used inside comments and inside character constants. 

Assembler Statements 

There are three kinds of assembler statements: 

1. Pseudo Operations, Sometimes called "pseudo ops," these statements are not 
translated into z-80 object code. They control various functions of the 
assembler itself, such as defining labels, reserving memory, and setting the 
programs origination address. Pseudo ops must begin in column 9. 

2. Commands. These are also directed at the assembler. The Series I Assembler 
has two assembler commands, *list on and *list off (described later). These 
commands must begin in column 1. 

3. z-80 Operations . These consist of a mnemonic (sometimes called an operation 
code or "opcode") sometimes followed by one, two or no operands. They 
are translated directly into object code. Some z-80 instructions translate into 
one byte of object code; others may translate into two, three, or four bytes. 
The opcode must begin in column 9. Tabbing one time moves to column 9. 

Special Terms and Abbreviations for Operands 

nnnn or nn Represents a number. For one-byte numbers, nn is used. For 
two-byte numbers, nnnn is used. (Two-byte numbers are 
assembled into two's complement binary values. First comes the 
least significant byte (lsb), then the most significant byte 
(msb)). A number may be any of these: 

Decimal number 

Hexadecimal number nnnim or mm. The suffix "h" indicates 
hexadecimal; if the number starts with a-f, prefix a to it, as 
in ofoh. 



Octal number: nnnnnQ or nnno. The suffix "q" or 
indicates octal. 



o 



27 



SERIES I EDITOR/ASSEMBLER 



Current address, "$" (The address in the program counter will 
be used in place of the $). 

Character constant: Any character inside single quotes. The 
constant is converted into its ascii character code. For example, 
'a' is converted into 65. 

Any numeric expression (see "Expressions"). 

Pseudo-Operations 

ORG nnnn 

(Originate) This sets the address reference counter. It determines where 
subsequent z-so code and data will reside in memory. If no org statement is 
given in your source program, the address reference counter will be set to 0. 

org should be used before any z-80 instructions or data storage pseudo ops. It 
may be repeated. The programs in this manual are ORGed at decimal 32512 
(hexadecimal 7F00). All subsequent org's are absolute. 

symbol EQU nnnn or nn 

(Equate) This assigns the value nnnn to the symbol. Each time the symbol is 
used as an operand in the source program, the assembler will replace it with 
nnnn. The equ statement may appear anywhere in the program. A particular 
symbol may be equated only once. 

label DEFL nnnn 

(Define label) This assigns a temporary value nnnn to the specified label. The 
value may be changed as often as required within the source program. 

END nnnn 

This indicates the end of a source program. If there are any following lines in 
the program, they will be ignored. The address nnnn sets the entry point to the 
program. If omitted, the entry to trsdos (disk systems) or basic (cassette 
systems) will be used. For details, see section 5. 

[label] DEFB nn 

This defines the contents of the current address to be nn. This pseudo op allows 
you to initialize the contents of one-byte storage locations used by the program. 
nn may be a one-byte value or a character string enclosed in single-quotes. 

[label] DEFH nnnn 

This defines the contents of the current two-byte address to be nnnn. This 
pseudo op allows you to initialize the contents of two-byte storage locations 
used by the program. 

[label] DEFB nn 

(Define storage) This reserves nn bytes of memory, starting at the current 
address. (The reference address will be incremented by nn before the next 



28 



USING THE ASSEMBLER 



source statement is assembled.) This pseudo op allows you to reserve space for 
buffers, parameters, etc. 

[label] DEFM string 

(Define message) This stores the specified string of characters, beginning at the 
current address. 

Assembler Commands 

The *list command allows you to suppress parts of a source listing. Error- 
messages and the offending source statements will still be listed. These 
commands are very useful when you are debugging long programs, because the 
parts of the program already corrected do not need to be listed. You may also 
want to use them to suppress the listing of long tables of data contained in 
programs (e.g., defm strings). 

The asterisk (*) portion of the *list on and *list off command must be in 
column one. 

*LIST OFF 

Has no effect on the assembly, but turns off the assembly listing. 

*LIST ON 

Has no effect on the assembly, but turns the assembly on again (after *list off). 

Using Expressions as Operands 

The assembler will accept an expression in place of any numeric operand. 
Expressions include symbols, numeric or string constants, and combinations 
of these using the arithmetic and logical operators listed below. 

+ and - Addition and subtraction. Example: 
LD HL»MID+80H 

— Negation. Example: 

LD HUUID-i 

LD HL >-l (0 understood) 

& Logical and. Example: 

LD A.(HL)&:0FH 

< Shift left or right. This operator shifts a value right or left by a 

specified number of bits, in this format: 

value < nn 

If nn is negative, the value is shifted to the right and zeroes fill on 
the left. If nn is positive, the value is shifted to the left and zeroes 
fill on the right. Example: 

LD A»UAL<2 



29 



SERIES I EDITOR/ASSEMBLER 



Shifts the val two bits to the left and fills with zeroes on the 
right. 



The Z-80 Instruction Set 

Section 6 is a full z-80 instruction set. The z-80 registers and flags available for 
the programmer's use and a description of the z-80 architecture is in Appendix F. 



30 



SAMPLE PROGRAMMING SESSION 



rt h we: 



ample rrogramming session 



In this section, we'll take you step by step through the Series I Editor/ 
Assembler. Our goal will be to create a machine-language subroutine that may 
be called from a basic program or the disk operating system of your computer. 

The machine-language we'll present is simple but useful. Given a source 
address, a destination address, and a length-value, it will copy a block of 
memory into another area of memory. Doing this with normal basic statements 
is slow. Doing this with machine-language is almost instantaneous. 



Creating the Source Program 

Start the Editor/ Assembler as explained in Section 2. Then type I (ENTER) to get 
into the line insertion mode. Now type in the following program, pressing 
(INTER) at the end of each line. (Remember to use tab to space from the end of 
one field to the start of the next field.) 



00100 
00110 
00120 
00130 
00140 
00150 
001G0 
00170 
001B0 
00190 
00200 
00210 
00220 
00230 



SUBROUTINE COPIES ONE BLOCK OF MEMORY TO ANOTHER AREA 
ON ENTRY, (SRC) = SOURCE ADDRESS 

(DST) = DESTINATION ADDRESS 
(LEN) = NUMBER OF BYTES TO MOVE 
32512 
HL»(SRC) 
DE,(DST) 
BC.(LEN) 



MOVE 



SRC 
DST 
LEN 



ORG 

LD 

LD 

LD 

LDIR 

RET 

DEFW 

DEFW 

DEFW 

END 



SOURCE ADDR. 
DESTINATION ADDR. 
LENGTH 



MOVE 



31 



^^£^^ ' ^ '1,' ^ ''' 



Press (BREAK) to quit inserting. Then type P #:* (ENTER) to see the entire source 
program. If there are any errors, use the edit mode (e command) to correct 
the line. 

If you have a printer, you may get a hard copy of the text by typing H #:* 
( ENTER) . 

Now we are ready to make a copy of the source program. We'll call it "move." 

Saving/Loading a Source Program (Tape Systems) 

Using a blank cassette tape, get the recorder ready to record. Type W MOVE 
(ENTER). Press (ENTER) again when you are ready to record. After the tape is 
recorded, the Editor/Assembler will return in the command mode (asterisk). It's 
a good idea to make a second tape copy. 

Now t ry reloading the program. Delete the text from memory by typing D #:* 
( ENTER) . Then rewind the recorder, prepare it to play, and type L MOVE ( ENTER) . 
Press (ENTER ) again when the recorder is ready to play. After the program has 
been loaded, the Editor will return in the command mode. Now skip to the 
paragraph titled, Trial Assembly. 

Saving/Loading a Source Program (Disk Systems) 



Type W MOVE (ENTER) . After the file is written, the Editor/Assembler will return 
in the command mode (asterisk). The file will be called move/src. 

Now try reloading the source program. Delete the text from memory by typing 
D #:* (ENTER). Then type L MOVE ( ENTER") . After the source program has been 
loaded, the Editor will return to the command mode, listing text and memory 
contents. 

Trial Assembly 

Now we are ready to see if the program can be assembled without errors. We'll 
use the no (no output) and we (wait on errors) switches for this purpose. 

The source program should be in memory. Type A ilMO »WE (ENTER ). The Editor/ 
Assembler will put the assembly listing on the screen. If any errors are found, 
the listing will be paused. An error message will appear directly above the 
offending line. Press any key to continue. 

If any assembly errors were found, use the edit mode to correct them, and try 
another trial assembly. 

If you have a printer, you may request a hard copy of the assembly listing. This 
will be preferable to the display listing, since most listings require more than 64 
columns per line. To output to the printer, type: A »N0 »LP ( ENTER) . 

Figure J shows the assembly listing generated by our sample program. We've 
added callouts to identify the various fields in the listing. 



32 



ta.Mg<igerJa<.'T.'. r .ti^ry„s....s"I3 



SA MPLE PROGRAMMING SESSION 

wmmmmmmmmmmmm 



immimmmmmmmmmmmmmammmmmmBasmaasBmamsm 



Memory 
Loc. 




Object 
Code 


Line 
Number 


Label 




Mnemonic 


Operand(s) 












00100 


i SUBROUTINE COPIES 


ONE 


BLOCK OF MEMORY 


TO ANOTHER AREA 








00110 


i ON 


ENTRY » 


(SRC) = 


SOURCE ADDRESS 












00120 


\ 




(DST) = 


DESTINATION ADDRESS 










00130 


5 




(LEN) = 


NUMBER OF BYTES 


TO 


MOUE 


7FB0 
7F00 
7F03 
7F07 




2A0E7F 

ED5B107F 

ED4B127F 


00140 
00150 
001B0 
00170 


MOUE 




ORG 
LD 
LD 
LD 




32512 
HL.(SRC) 
DE.(DST) 
BC.(LEN) 




i SOURCE ADDR. 

! DESTINATION ADDR 

i LENGTH 


7F0B 




EDB0 


00180 






LDIR 










7F0D 




C9 


00130 






RET 










7F0E 




0000 


00200 


SRC 




DEFW 











7F10 




0000 


00210 


DST 




DEFW 











7F12 




0000 


00220 


LEN 




DEFW 











7F00 






00230 






END 




MOUE 






00000 




Total Er ro rs 


















LEN 


7F12 




















DST 


7F10 




















SRC 


7F0E 




















MOUE 


7F00 





















Symbol Table 
Figure 1 . Sample Assembly Listing 

Here are a few comments on the source program (line references are to column 
3 of the listing): 

Line 140 sets the origination address of the program. We've chosen an address 
near the top of memory in a 16K ram system. If you change this address, be sure 
to make the appropriate changes in the basic calling program (presented later). 

Line 230 ends the program. Since we gave an operand (move), the Editor/ 
Assembler will store the value of move as the entry address to the program. If 
we had omitted an operand here, the entry address to the program would have 
been set to address ooooh. (More later.) 



Object Code Output 

After confirming that the program can be assembled without errors, we are 
ready to create the object file on tape or disk. We'll use an assemble command 
that outputs object code only. 



*w&sw.--i 



33 



SERIES I EDITOR/ASSEMBLER 



Tape Systems 

Using a blank tape, prepare the recorder to record. Type A M0VE>NL>NS (ENTER) . 
Press (ENTER) again when ready. The Editor/Assembler will write out the object 
tape. It's a good idea to repeat this process to get a second tape copy. 

Disk Systems 

Type A MOVE >NL »NS (ENTER) . The Editor/Assembler will create an object file 
named move/cmd. 

Running the Sample Program 

Our sample program, move, may be executed as a basic subroutine or as an 
independent program. 

First, we'll try it as a basic subroutine. 

Tape Systems (Level II and Mod III only — will not execute in a 
Level I machine) 

Start basic and answer the memory size question by typing 3251 1 (ENTER) . This 
will keep basic from using the area where the subroutine will reside. 

Now load the subroutine: 



Type system (ENTER) . Prepare the recorder to play the object tape, then type 
move (ENTER) . After the program has been loaded, the *? will return. Press 
(BREAK) to return to basic. Now type in the basic program given in Listing #1. 

(Page 36) 

Run the program. Specify any source address, and specify a destination between 
15360 and 16383. Specify any length from 1 to 1024. However, the destination 
+ length must not exceed 16384. 

The program will copy a block of memory beginning at the source onto video 
memory beginning at the destination. The number of bytes copies will be the 
length value. 

Disk Systems 

Start trsdos. Under trsdos ready, load the subroutine by typing LOAD 
MOVE/CMD. 

Start basic. Answer the memory size question by typing 3251 1 (ENTER) . This 
will keep basic from using the memory where move resides. 

Now type in the program given in Listing 2. (Page 36) 

Run the program. Specify any source address, and specify a destination between 
15360 and 16383. Specify any length from 1 to 1024. However, the destination 
+ length must not exceed 16384. 

The program will copy a block of memory beginning at the source onto video 
memory beginning at the destination. The number of bytes copied will be the 
length value. 



34 



SAMPLE PROGRAMMING SESSiOI 






Executing a Machine-Language Program Directly 

move is a subroutine called from a basic program. However, you can also 
execute machine-language programs created with the Editor/ Assembler. 

Disk Systems 

Under trsdos ready, type in the program name and press (ENTER) . The program 
will be loaded and executed, starting at the address specified in the end 
statement of the original source listing (e.g. , line 230 of our sample program). 
Don't use our sample program this way; it was designed to be called from 
basic only. 

Tape Systems (Level II and Mod III BASIC) 

Load the program using the system command, as explained previously. After 
the program has been loaded from tape, the *? will reappear. Don't press 
(ENTER) . Press / (ENTER) instead. The Computer will begin executing the program 
at the address specified in the end statement of the original source listing (e.g., 
line 230 of our sample program). 



Alternatively, you may type / address (ENTER) to override this entry address. 

(Don't try this with move; that subroutine should only be called from a basic 
program like the one we presented.) 

Tape Systems (Level I users) 

You may load the program using the Level I 'System Loader' tape that came 
with your edtasm. This is accomplished by typing CLOAD. A prompt 
"cassette ready" will appear on the screen. When the tape is ready to load 
press (ENTER) . Your object program will load at this time. The Computer will 
begin executing your program at the address specified in the end statement. 

You may write your own "System Loader" and put it at the beginning of each 
Level I program. (Refer to Appendix B) Tapes loaded into Level I with the 
"System Loader" must be ORGed above 4500H and be created by edtasm. 

10 POKE 16526,0; POKE 16527,127 

20 SRC = 32526 

30 DST = 32528 

40 LN = 32530 

50 CLS 

60 INPUT "SOURCE" i S 

70 INPUT "DESTINATION"! D 

80 INPUT "LEN" ! L 

90 IF (D< 15360) OR (DME383) THEN 230 

100 ML = S: MM = SRC: G0SUB 190 

110 IF (D< 15360) OR (D> 16383) THEN 230 

120 IF D+L > 16384 THEN 240 

130 VL = D: MM = DST: G0SUB 190 

140 0L = L: MM = LN: G0SUB 190 



I EDITOR/ ASSEMBLER 

■■■■■■■■—— 



150 X = USR(0) 

1G0 IF INKEY$="" THEN 160 

170 GOTO 50 

1B0 'BREAK NUMBER INTO MSB* LSB 

190 MSX = VL/256; LSI = VL - (MSI * 25B) 

200 'PUT DATA INTO MEMORY 

210 POKE MM, LSI; POKE MM+lt MS% 

220 RETURN 

230 PRINT "INVALID DESTINATION"; STOP 

240 PRINT "DATA BLOCK EXCEEDS END OF VIDEO RAM": STOP 

Listing #/. 

10 DEFUSR = &H7F00 

20 SRC = &H7F0E 

30 DST = &H7F10 

40 LN = &H7F12 

50 CLS 

G0 INPUT "SOURCE" ! S 

70 INPUT "DESTINATION" 5 D 

80 INPUT "LEN"! L 

90 IF (D< 15360) OR (D>1G383) THEN 230 

100 1.1 L = S: MM= SRC: GOSUB 190 

110 IF (DM5360) OR (DM6383) THEN 230 

120 IF D+L > 1G384 THEN 240 

130 VL = D: MM = DST: GOSUB 190 

140 VL = L: MM = LN: GOSUB 190 

150 X = USR(0) 

160 IF INKEY*="" THEN 160 

170 GOTO 50 

180 'BREAK NUMBER INTO MSB. LSB 

190 MSI = VL/25G: LSI = VL - (MS'/, * 256) 

200 'PUT DATA INTO MEMORY 

210 POKE MM, LSI: POKE MM+1 » MSX 

220 RETURN 

230 PRINT "INVALID DESTINATION": STOP 

240 PRINT "DATA BLOCK EXCEEDS END OF VIDEO RAM": STOP 



Listing #2. 



36 



THE Z-8Q INSTRUCTION SET 



Part Six: 



Notation and Other Conventions 

This section includes a detailed description of all the z-80 assembly language 
instructions. The first line of each of these pages shows the assembly language 
opcode mnemonic followed by its operand(s). Some instructions have no 
operands at all. Other instructions have one or two operands. Anything which 
is capitalized should be copied exactly when you use the editor to write the 
assembly language source code. Anything shown in lowercase letters will be 
replaced by an appropriate register, number, or label. For example, the first 
instruction described in the eight-bit load group is: 

LD r,r' 

ld is the mnemonic for the Load instruction. If you wish to move the contents 
of register h into register a, the actual source code is 

LD A,H 

This should be read as "load register a with the contents of register h." 

A detailed explanation of the operand notation is given below, but in general 
you should note that single lowercase letters are used for eight-bit numbers or 
registers and double lowercase letters are used for 16-bit numbers or registers. 
Also note that parentheses around a register pair indicates that the register pair is 
to be used as a pointer to a memory location. For example, the instruction inc 
hl means that 1 is to be added to the hl register pair. The instruction inc (hl) 
means that 1 will be added to a number in memory whose address is found in 
register pair hl. 

Symbol Specifies one of the registers 

r A, B,C, D, E, H, 01' L. 

Symbol Specifies a register pair 

qq BC, DE, hl, or AF 

SS BC, DE, HL, OrSP 

dd BC, DE. hl. orsp 

pp BC, DE, IX, or SP 

rr bc, de, ix, or sp 



37 



SERIES I EDITOR/ASSEMBLER 



Symbol Specifies a number or symbol in the range 

n to 255 (one byte) 

nn to 65535 (two bytes) 

d -128 to 127 (one byte) 

e -126 to 129 (one byte) 

Symbol Specifies any of the following 

s r, n, (hl), (ix + d), or (iy + d) 

m r, (hl) (ix + d), or (iy + d) 

(nn) Specifies the contents of memory location nn 

b Specifies an expression in the range (0,7) 

cc Specifies the state of the Flags for conditional jr, jp, call and 

ret instructions 

Instruction Format Examples With Explanation 

Format Example 1 



Operation: r<0 (HL) 

This is the shorthand description of the instruction. The arrow indicates that data 
is moved into register r. 

When you write the assembly language code, the lowercase r will be replaced 
by A, B,C, D, E, H or L. 

Format: 

Mnemonic: LD Operands: r,(HL) 

Object Code: 



! ! ! ! ! ! ! 

1 r r r 1 1 

I I I I I I l 



The object code for this instruction is one byte long. To figure out the object 
code, replace bits 3, 4 and 5 with the appropriate numbers from the table. For 
example: 

Source Code Object Code 

LD A,(HL) 01111110 

LD B,(HL) 01000110 

LD C,(HL) 01001110 



38 



THE Z-80 INSTRUCTION SET 



This instruction uses two machine (M) cycles. The first machine cycle consists 
of four timing (T) states and the second machine cycle consists of three T states 
for a total of seven T states. In the TRS-80 one T state takes .5636714 
microseconds because the clock speed is 1.774038 MHz, for Model I, 4 MHz 
for Model If and 2.02752 MHz for Model III. The execution time (E.T.), in 
microseconds, is calculated for the TRS-80. (One microsecond is 10 ~ 6 seconds 
or 1/1,000,000 of a second.) 

Description: 

The eight-bit contents of memory location (HL) are loaded into register r, where 
r identifies register A, B, C, D, E, H or L, assembled as follows in the object 
code: 



Register 


r 


A 


111 


B 


000 


C = 


001 


D 


010 


E 


011 


H 


100 


L = 


101 


M cycles: 2 


T states: 7(4,3) 



4MHzE.T: 1.75 
Condition Bits Affected: None 

Example: 

If register pair HL contains the number 75A1H, and memory address 75 A1H 
contains the byte 58H, the execution of 

LD C, (HL) 

will result in 58H in register C. 

Format Example 2 

JP cc 3 nn 

Operation: IF CC TRUE, PC<inn 

The jump is made only if the condition cc is true. The arrow indicates that the 
number nn is moved into the program counter PC. This will cause the program 
to jump to address nn. 

When you write the assembly language code, cc will be replaced by one of the 
following: NZ, Z, NC, C, PO, PE, P or M. nn will be replaced by a number 
from to 65535 or a label. 



39 



SERIES I E DITOR/ASSEMBLER 

Format: 

Mnemonic: JP Operands: cc, nn 

Object Code: 



1 


1 


cc 


cc 


cc 





1 









n 


n 


n 


n 


n 


n 


n 


n 






n 


n 


n 


n 


n 


n 


n 


n 



Note: The first n operand in this assembled object code is the low order byte of 
a two-byte memory address. 

The object code for this instruction is three bytes long. To figure out the object 
code, replace bits 3, 4 and 5 of the first byte with the appropriate number from 
the table. The second two bytes of the object code are the address being jumped 
to. For example: 



Object Code 

11000010 C2H 
00000000 00H 
11111111 FFH 
11111010 FAH 
02H 
) 10000 10H 



Source Code 
JP NZ, 0FF00H 

JP M, 1002H 



Note that the low order, or right hand byte, of the address comes first in the 
object code. 

Description: 

If condition cc is true, the instruction loads operand nn into register pair PC 
(Program Counter), and the program continues with the instruction beginning at 
address nn. If condition cc is false, the Program Counter is incremented as 
usual, and the program continues with the next sequential instruction. Condition 
cc is programmed as one of eight status bits which correspond to condition bits 
in the Flag Register (register F). These eight status bits are defined in the table 
below which also specifies the corresponding cc bit fields in the assembled 
object code. 

The Relevant Flag column shows the value the flag must have if the jump is to 
occur. 



40 



THE Z-80 INSTRUCTION SET 



Relevant 
cc Condition Flag 

000 NZ nonzero Z =0 

001 Zzero Z = 1 

010 NC no carry C =0 

011 Ccairy C = 1 

100 PO parity odd or no overflow P/V = 

101 PE parity even or overflow P/V = 1 

110 P sign positive S =0 

111 M sign negative S = 1 

M cycles: 3 T states: 10(4,3,3) 4 MHz E.T.: 2.50 
Condition Bits Affected: None 

Example: 

If the Carry Flag (C flag in the F register) is set and the contents of address 1520 
are 03H, after the execution of 

JP C,1520H 

the Program Counter will contain 1520H, and on the next machine cycle the 
CPU will fetch from address 1520H the byte 03H. In other words, program 
execution jumps to the instruction at 1520H. 

Format Example 3 

CP1R 

Operation: A -(HL), HL0HL+ 1, BC<)BC - 1 

The shorthand description indicates that three different things are happening: 

1 . BC is decremented 

2. HL is incremented 

3. A byte in memory is subtracted from the A register (but the results are not 
saved). 

Format: 

Mnemonic: CPIR Operands: 



41 



SERIES I EDITOR/ASSEMBLER 



Object Code: 



1 


1 


1 





1 


1 





1 




1 





1 


1 











1 



ED 



Bl 



The assembly language instruction has no operands. 
The object code is two bytes long. 

Description: 

The contents of the memory location addressed by the HL register pair is 
compared with the contents of the Accumulator. In case of a true compare, a 
condition bit is set. The HL is incremented and the Byte Counter (register 
pair BC) is decremented. If decrementing causes the BC to go to zero or if 
A = (HL), the instruction is terminated. If BC is not zero and A i= (HL), the 
program counter is decremented by 2 and the instruction is repeated. Note that if 
BC is set to zero before the execution, the instruction will loop through 64K 
bytes, if no match is found. Also, interrupts will be recognized after each data 
comparison. 

ForBC*0andA*(HL): 

M cycles: 5 T states: 21(4,4,3,5,5) 4 MHz E.T.: 5.25 

ForBC = 0orA = (HL): 

M cycles: 4 T states: 16(4,4,3,5) 4 MHz EX: 4.00 

The total execution time of this instruction depends on how long it takes to find 
the byte being searched for and the length of the block being searched. If the 
instruction loops three times before BC = or A = (HL), then there will be 58 
(2x21 + 16) timing (T) states executed. 

Condition Bits Affected: 

S: Set if result is negative; reset otherwise 

Z: Set if A = (HL); reset otherwise 

H: Set if borrow from Bit 4; reset otherwise 

P/V: Set if BC becomes zero; reset otherwise 

N: Set 

C: Not affected 



Example: 

If the HL register pair contains 111 1H, the Accumulator contains F3H, the Byte 
Counter contains 0007H, and memory locations have these contents: 



(1111H) 
(1112H) 
(1113H) 



52H 
00H 
F3H 



42 



THE Z-80 INSTRUCTION SET 



then after the execution of 

CPIR 

the contents of register pair HL will be 1114H, the contents of the Byte Counter 
will be 0004H. Since BC^0, the P/V flag is still set. This means that it did not 
search through the whole block before the instruction stopped. Since a match 
was found, the Z flag is set. 

The CPIR instruction will affect five of the six condition codes. 



43 



THE Z-80 INSTRUCTION SET 

— — — — . — ~ — ~ : : : ■ ~ : : : ~ — — ■- -- i 



Z-80 Instruction Set 
Table of Contents 



8 Bit Load Group 47 

16 Bit Load Group 65 

Exchange, Block Transfer 

and Search Group 87 

8 Bit Arithmetic and Logical Group 105 

General Purpose Arithmetic 

and CPU Control Groups 135 

16 Bit Arithmetic Group 141 

Rotate and Shift Group 151 

Bit Set, Reset 

and Test Group 177 

Jump Group 189 

Call and Return Group 201 

Input and Output Group 211 



45 



8 BIT LOAD GROUP 



8 Bit Load Group 



LD r,r' 



LoaD 



Operation: r<Jr' 

Format: 

Mnemonic: LD Operands: r, r' 



Object Code: 



i i r t^ i i i — 

1 r r r r' r' r' 

I L__J I l l l 



Description: 

The contents of any register r' are loaded into any other register r. Note: r, r' 
identifies any of the registers A, B, C, D, E, H, or L, assembled as follows in 
the object code: 



Register 


r, r' 




A = 


111 




B = 


000 




C = 


001 




D = 


010 




E = 


011 




H = 


100 




L = 


101 




M cycles: 1 


T states: 4 


4MHzE.T.: 1.0 



Condition Bits Affected: None 

Example: 

If the H register contains the number 8 AH, and the E register contains 10H, the 
instruction 

LD H,E 

would result in both registers containing 10H. 



47 



SERIES I EDITOR/ASSEMBLER 



Biaa»»iBaB»wig^^ 



a»ttii8ti 



LDr,n 

Operation: Y <0 fl 

Format: 

Mnemonic: LD Operands: r, n 



LoaD 



Object Code: 










I i i 
r r 

i i i 


r 


1 


1 







1 1 I 

n n n n 

i i i 


n 


n 


n 


n 



Description: 

The eight-bit integer n is loaded into any register r, where r identifies register A, 
B, C, D, E, H or L, assembled as follows in the object code: 



Register 


r 


A = 


111 


B 


000 


C 


001 


D 


010 


E 


011 


H = 


100 


L = 


101 


M cycles: 2 


T states: 7(4,3) 



4 MHz EX: 1.75 



Condition Bits Affected: None 

Example 1: 

After the execution of 

LD E.A5H 

the contents of register E will be A5H. 

Example 2: 

After the execution of 

LD A,0 

register A will contain zero. 



48 



EZS 



8 BIT LOAD GROUP 



Operation: f(l(HL) 



Format: 
Mnemonic: LD 

Object Code: 



Operands: r, (HL) 



I | 1 1 r 

1 r r r 

I I I I L 



LoaD 



Description: 

The eight-bit contents of memory location (HL) are loaded into register r, where 
r identifies register A, B, C, D, E, H or L, assembled as follows in the object 
code: 



Register 


r 






A 


111 






B 


000 






C = 


001 






D = 


010 






E 


011 






H 


100 






L 


101 






M cycles: 2 


T states: 7(4,3) 


4 MHz EX: 


1.75 



Condition Bits Affected: None 

Example: 

If register pair HL contains the number 75A1H, and memory address 75A1H 
contains the byte 58H, the execution of 

LD C,(HL) 

will result in 58H in register C. 



r 5 (IX + d 



LoaD 



Operation: r<l(IX + d) 

Format: 

Mnemonic: LD Operands: r, (IX + d) 



49 



SERIES 1 EDITOR/ASSEMBLER 



Object C 


"ode 












1 1 





1 


1 


1 





1 






1 


r 


r 


r 


1 


1 









d d 


d 


d 


d 


d 


d 


d 



DD 



Description: 

The operand (IX + d) (the contents of the Index Register IX summed with a 
displacement integer d) is loaded into register r, where r identifies register A, B, 
C, D, E, H or L, assembled as follows in the object code: 



Register 


r 


A = 


111 


B = 


000 


C = 


001 


D = 


010 


E 


011 


H = 


100 


L = 


101 



M cycles: 5 T states: 19(4,4,3,5,3) 4 MHz E.T.: 4.75 
Condition Bits Affected: None 

Example: 

If the Index Register IX contains the number 25AFH, the instruction 

LD B,(IX+19H) 

will cause the calculation of the sum 25AFH+ 19H, which points to memory 

location 25C8H. If this address contains byte 39H, the instruction will result in 

register B also containing 39H. 

A typical use of this instruction is shown below. If TABL is a location in 

memory this program will load the first four bytes of the table into registers A, 

B,CandD. 



LD 


IX, TABL 


IX points to the table 


LD 


A, (IX + 0) 


Load first byte 


LD 


B, (IX+1) 


Load second byte 


LD 


C, (IX + 2) 


Load third byte 


LD 


D, (IX + 3) 


Load fourth byte 



50 



8 BIT LOAD GROUP 



LD r,(IY + d) 



LoaD 



Operation: r(l(l 

Format: 
Mnemonic: LD 

Object Code: 


Y + d) 

Operands: r, (IY + d) 


1 1 1 

1111 

i i i 


1 1 1 

110 1 

I i i 


FD 








i i I 

1 r r 

i i i 


1 1 1 

r 1 1 

i i i 










1 1 1 

d d d d 

i i i 


1 1 1 

d d d d 

i i i 




Description: 







The operand (IY + d) (the contents of the Index Register IY summed with a 
two's complement displacement integer d) is loaded into register r, where r 
identifies register A, B, C, D, E, H, or L, assembled as follows in the object 
code: 



gister 


r 


A = 


111 


B 


000 


C 


001 


D = 


010 


E 


011 


H = 


100 


L = 


101 



M cycles: 5 T states: 19(4,4,3,5,3) 4 MHz E.T.: 4.75 
Condition Bits Affected: None 

Example: 

If the Index Register IY contains the number 25AFH, the instruction 

LD B,(IY+19H) 

will cause the calculation of the sum 25AFH+ 19H, which points to memory 
location 25C8H. If this address contains byte 39H, the instruction will result in 
register B also containing 39H. 



51 



SERIES 1 EDITOR/ASSEMBLER 



LD (HL) 5 r LoaD 

Operation: (HL)(ir 

Format: 

Mnemonic: LD Operands: (HL), r 

Object Code: 



1 ! ! j ! , ! 

1 1 1 r r r 

i i i I l I l 



Description: 

The contents of register r are loaded into the memory location specified by the 
contents of the HL register pair. The symbol r identifies register A, B, C, D, E, 
H or L, assembled as follows in the object code: 



Register 


r 




A 


= 


111 




B 


= 


000 




C 


= 


001 




D 


= 


010 




E 


= 


011 




H 


= 


100 




L 


= 


101 




M eye 


les: 2 


T states: 7(4,3) 


4MHzE.T: 1.75 



Condition Bits Affected: None 

Example: 

If the contents of register pair HL specify memory location 2146H, and the B 
register contains the byte 29H, after the execution of 

LD (HL),B 

memory address 2146H will also contain 29H. 



D(iX + d),r LoaD 

Operation: (IX + d)<ir 



Format: 

Mnemonic: LD Operands: (IX + d), r 



52 



^ 8 BIT LOAD GROUP 



Object Code: 










i I I 

110 1 

i i i 


1 


1 





1 




I I 1 

111 

1 1 1 





r 


r 


r 




d d d d 

i i i 


d 


d 


d 


d 



DD 



Description: 

The contents of register r are loaded into the memory address specified by the 
contents of Index Register IX summed with d, a two's complement displacement 
integer. The symbol r identifies register A, B, C, D, E, H or L, assembled as 
follows in the object code: 



gister 


r 


A 


111 


B 


000 


C = 


001 


D = 


010 


E = 


011 


H 


100 


L 


101 


cycles: 5 


Ts 



T states: 19(4,4,3,5,3) 4 MHz E.T.: 4.75 



Condition Bits Affected: None 

Example: 

If the C register contains the byte 1CH, and the Index Register IX contains 
3100H, then the instruction 

LD (IX + 6H), C 

will perform the sum 3100H + 6H and will load 1CH into memory location 
3106H. 



LD(IY+d) ? r 

Operation: (IY+d)<ir 



LoaD 



Format: 
Mnemonic: LD 



Operands: (lY+d), 



53 



SERIES I EDITOR/ASSEMBLER 



Object C 


:ode 












1 1 

i 


1 


1 


1 


1 





1 






i 

1 

i 


1 


1 





r 


r 


r 






1 
d d 


d 


d 


d 


d 


d 


d 



FD 



Description: 

The contents of register r are loaded into the memory address specified by the 
sum of the contents of the Index Register IY and d, a two's complement 
displacement integer. The symbol r is specified according to the following table. 



gister 


r 


A = 


111 


B 


000 


C 


001 


D = 


010 


E 


011 


H = 


100 


L = 


101 



M cycles: 5 T states: 19(4,4,3,5,3) 4 MHz E.T.: 4.75 
Condition Bits Affected: None 

Example: 

If the C register contains the byte 48H, and the Index Register IY contains 
2A11H, then the instruction 

LD (IY+4H),C 

will perform the sum 2A11H + 4H, and will load 48H into memory location 

2A15. 



LD (HL) 5 n 

Operation: (Hl_) <) II 

Format: 

Mnemonic: LD Operands: (HL), n 



LoaD 



54 



______ 8 BIT LOAD GROUP 



Object Code: 









1 


1 





1 


1 







n 


n 


n 


n 


n 


n 


n 


n 



36 



Description: 

Integer n is loaded into the memory address specified by the contents of the HL 
register pair. 

M cycles: 3 T states: 10(4,3,3) 4 MHz E.T.: 2.50 
Condition Bits Affected: None 

Example: 

If the HL register pair contains 4444H, the instruction 

LD (HL),28H 

will result in the memory location 4444H containing the byte 28H. 



LD (IX + d) 3 n 

Operation: (IX + d)<in 

Format: 

Mnemonic: LD Operands: (IX + d), n 



Load 



Object Code: 



1 


1 





1 


I 


1 





1 
















1 


1 





1 


1 















d 


d 


d 


d 


d 


d 


d 


d 












n 


n 


n 


n 


n 


n 


n 


n 



DD 



36 



55 



SERIES I EDITOR/ASSEMBLER 



n _ 



•a _- •■ i- ,j.i 



Description: 

The n operand is loaded into the memory address specified by the sum of the 
contents of the Index Register IX and the two's complement displacement 
operand d. 

M cycles: 5 T states: 19(4,4,3,5,3) 4 MHz E.T.: 4.75 

Condition Bits Affected: None 

Example: 

If the Index Register IX contains the number 2 19AH the instruction 

LD (IX + 5H),5AH 

would result in the byte 5 AH in the memory address 219FH. 
(219FH = 219AH + 5H.) 



LD(IY+d),n 

Operation: (IY+d)<in 

Format: 

Mnemonic: LD Operands: (IY+d), n 



Object Code: 



1 


1 


1 


1 


1 


1 





1 












1 


1 





1 


1 









d 


d 


d 


d 


d 


d 


d 


d 






n 


n 


n 


n 


n 


n 


n 


n 



FD 



36 



LoaD 



Description: 

Integer n is loaded into the memory location specified by the contents of the 
Index Register summed with a two's complement displacement integer d. 

M cycles: 5 T states: 19(4,4,3,5,3) 4 MHz E.T.: 4.75 
Condition Bits Affected: None 



56 



8 BIT LOAD GROUP 



Example: 

If the Index Register IY contains the number A940H, the instruction 

LD (IY+ 10H),97H 

would result in byte 97H in memory location A950H. 



D A,(BC) LoaD 

Operation: A <1 (BC) 



Format: 

Mnemonic: LD Operands: A, (BC) 

Object Code: 

0A 



I | | | , 1 1 

10 10 

I I I I I I I 



Description: 

The contents of the memory location specified by the contents of the BC register 
pair are loaded into the Accumulator. 

M cycles: 2 T states: 7(4,3) 4 MHz E.T.: 1.75 
Condition Bits Affected: None 

Example: 

If the BC register pair contains the number 4747H, and memory address 4747H 
contains the byte 12H, then the instruction 

LD A,(BC) 

will result in byte 12H in register A. 

L=LJ r\ J \LJn.J LoaD 

Operation: A <0 (DE) 

Format: 

Mnemonic: LD Operands: A, (DE) 



57 



SERIES I EDITOR/ASSEMBLER 



Object Code: 












1 


1 





1 






1A 



Description: 

The contents of the memory location specified by the register pair DE are loaded 
into the Accumulator. 

M cycles: 2 T states: 7(4,3) 4 MHz E.T.: 1.75 
Condition Bits Affected: None 

Example: 

If the DE register pair contains the number 30A2H and memory address 30A2H 
contains the byte 22H, then the instruction 

LD A,(DE) 

will result in byte 22H in register A. 



LD A 5 (nn) 

Operation: A <l(nn) 

Format: 

Mnemonic: LD Operands: A, (nn) 



LoaD 



Object Code: 












III 

1 

i i i 


1 


1 





1 







l I 1 

n n n 

i i i 


n 


n 


n 


n 


n 




1 1 1 

n n n 

i i i 


n 


n 


n 


n 


n 



3A 



Description: 

The contents of the memory location specified by the operands nn are loaded 
into the Accumulator. The first n operand is the low order byte of a two-byte 
memory address. 

M cycles: 4 T states: 13(4,3,3,3) 4 MHz E.T.: 3.25 



58 



_______ 8 BIT LOAD GROUP 



Condition Bits Affected: None 

Example: 

If the contents of memory address 8832H is byte 04H, after the instruction 

LD A,(8832H) 

byte 04H will be in the Accumulator. 

LD (BC),A LoaD 

Operation: (BC)<JA 

Format: 

Mnemonic: LD Operands: (BC), A 

Object Code: 

I 1 1 1 1 

02 





















1 






Description: 

The contents of the Accumulator are loaded into the memory location specified 
by the contents of the register pair BC. 

M cycles: 2 T states: 7(4,3) 4 MHz EX: 1.75 
Condition Bits Affected: None 

Example: 

If the Accumulator contains 7 AH and the BC register pair contains 1212H the 
instruction 

LD (BC),A 

will result in 7AH being in memory location 1212H. 

Li-\ /r~\i^\ a 

Operation: (DE)<lA 

Format: 

Mnemonic: LD Operands: (DE), A 



59 



SERIES I EDITOR/ASSEMBLER 



Object Code: 












1 








1 






12 



Description: 

The contents of the Accumulator are loaded into the memory location specified 
by the DE register pair. 

M cycles: 2 T states: 7(4,3) 4 MHz E.T.: 1.75 
Condition Bits Affected: None 

Example: 

If the contents of register pair DE are 1128H, and the Accumulator contains byte 

A0H, the instruction 

LD (DE),A 

will result in A0H being in memory location 1128H. 



LD (nn),A 

Operation: (nn)<l A 

Format: 

Mnemonic: LD Operands: (nn), A 



LoaD 



Object C 


:ode 


; 










1 



1 


1 


1 

1 








1 







1 

n n 

i 


n 


1 

n 

I 


n 


n 


n 


n 




I'- 
ll n 
1 


n 


1 
n 

1 


n 


n 


n 


n 



32 



Description: 

The contents of the Accumulator are loaded into the memory address specified 
by the operands nn. The first n operand in the assembled object code above is 
the low order byte of nn. 

M cycles: 4 T states: 13(4,3,3,3) 4 MHzE.T.: 3.25 



60 



8 BIT LOAD GROUP 



Condition Bits Affected: None 

Example: 

If the contents of the Accumulator are byte D7H, after the execution of 

LD (3141H),A 

D7H will be in memory location 3141H. 



LDA,I 

Operation: A <) I 

Format: 
Mnemonic: LD 



Operands: A, I 



Object Code: 








1 1 1 
1110 


1 


1 


1 

L 1 




l II 
10 1 

1 1 1 





1 


1 1 

1 



ED 



57 



LoaD 



Description: 

The contents of the Interrupt Vector Register I are loaded into the Accumulator. 
M cycles: 2 T states: 9(4,5) 4 MHz E.T.: 2.25 

Condition Bits Affected: 



S: 


Set if I-Reg. is negative; reset otherwise 


Z: 


Set if I-Reg. is zero; reset otherwise 


H: 


Reset 


P/V: 


Contains contents of IFF2 


N: 


Reset 


C: 


Not affected 



Note: If an interrupt occurs during execution of this instruction, the Parity flag 
will contain a 0. 

Example: 

If the Interrupt Vector Register contains the byte 4 AH, after the execution of 

LD A,I 

the accumulator will also contain 4AH. 



61 



SERIES I EDITOR/ASSEMBLER 



i n a r 

Operation: A <^ R 

Format: 

Mnemonic: L.D Operands: A, R 

Object Code: 





1 


1 


1 





1 


1 





1 







1 





1 


1 


1 


1 


1 



ED 



5F 



LoaD 



Description: 

The contents of Memory Refresh Register R are loaded into the Accumulator. 
M cycles: 2 T states: 9(4,5) 4 MHz E.T. : 2.25 

Condition Bits Affected: 



S: 


Set if R-Reg. is negative; reset otherwise 


Z: 


Set if R-Reg. is zero; reset otherwise 


H: 


Reset 


P/V: 


Contains contents of IFF2 


N: 


Reset 


C: 


Not affected 



Example: 

If the Memory Refresh Register contains the byte 4 AH, after the execution of 

LD A,R 

the Accumulator will also contain 4AH. 



LDI,A 

Operation: I (} A 

Format: 

Mnemonic: L-D Operands: I, A 



LoaD 



62 



8 BIT LOAD GROUP 



1 


1 


1 





1 


1 





1 







1 











1 


1 


1 



ED 



47 



Description: 

The contents of the Accumulator are loaded into the Interrupt Control Vector 
Register, I. 

M cycles: 2 T states: 9(4,5) 4 MHz E.T. : 2.25 
Condition Bits Affected: None 

Example: 

If the Accumulator contains the number 81H, after the instruction 

LD I,A 

the Interrupt Vector Register will also contain 81H. 



I no a 

Operation: R<)A 

Format: 

Mnemonic: LD Operands: R, A 

Object Code: 



1110 110 1 

l l l I I I I 



10 1111 

I I I I I I I 



ED 



4F 



LoaD 



Description: 

The contents of the Accumulator are loaded into the Memory Refresh register R. 

M cycles: 2 T states: 9(4,5) 4 MHz E.T. : 2.25 

Condition Bits Affected: None 



63 



SERIES I EDITOR/ASSEMBLER 



Example: 

If the Accumulator contains the number B4H, after the instruction 

LD R,A 

the Memory Refresh Register will also contain B4H. 



64 



16 BIT LOAD GROUP 



r — T^— — ■ — — — — — -— r— -— 7-t— --;-: ^^ -—rTrTr-^T^y^^:: . , r ^ j^^jy^TTT^ 



LoaD 



Operation: dd (l nn 

Format: 

Mnemonic: LD Operands: dd, nn 



Object Code: 










l I I 
d d 

i i i 











l 








I I I 

n n n n 

i i i 


n 


n 


n 


n 








n n n n 

i i i 


n 


n 


n 


n 



Description: 

The two-byte integer nn is loaded into the dd register pair, where dd defines the 
BC, DE, HL, or SP register pairs, assembled as follows in the object code: 

Pair dd 

BC 00 

DE 01 

HL 10 

SP 11 

The first n operand in the assembled object code is the low order byte. 

M cycles: 3 T states: 10(4,3,3) 4 MHz E.T.: 2.50 

Condition Bits Affected: None 

Example: 

After the execution of 

LD HL,5000H 

the contents of the HL register pair will be 5000H. 



w m 



65 



SERIES I EDITOR/ASSEMBLER 



After the execution of 

LD BC.2501H 

the BC register will contain 250 1H. 



LD IX,nn 



LoaD 



Operation: IX<inri 

Format: 

Mnemonic: LD Operands: IX, nn 

Object Code: 



1 


1 





1 


1 


1 





1 












1 














1 








n 


n 


n 


n 


n 


n 


n 


n 






n 




n 


n 


n 


n 


n 


n 


n 



DD 



21 



Description: 

Integer nn is loaded into the Index Register IX. The first n operand in the 
assembled object code above is the low order byte. 

M cycles: 4 T states: 14(4,4,3,3) 4 MHz E.T.: 3.50 



Condition Bits Affected: None 

Example: 

After the instruction 

LD IX.45A2H 

the Index Register will contain integer 45A2H. 



66 



16 BIT LOAD GROUP 

I" ' ". ."" , '__'_ . ' Z.~ _"_ LI 1 .'- . 1 "L~ "Z.-Z-. "Z iL-liLiT ."IZ1I ™_ Lj.IL ILL _'_L - t~t ""-''.I 



LoaD 



Operation: IY(inn 

Format: 

Mnemonic: LD Operands: IY, nn 



Object Code: 










1 
1 1 

i 


1 

1 1 

I 


1 


1 





1 






I 



i 


1 











1 








n n 


n n 


n 


n 


n 


n 








n n 

1 


n n 


n 


n 


n 


n 



FD 



21 



Description: 

Integer nn is loaded into the Index Register IY. The first n operand in the 
assembled object code above is the low order byte. 

M cycles: 4 T states: 14(4,4,3,3) 4 MHz E.T.: 3.50 
Condition Bits Affected: None 

Example: 

After the instruction: 

LD IY.7733H 

the Index Register IY will contain the integer 7733H. 



LD HL 5 (nn 



Operation: H <i (nn + 1 ) , L <i (nn) 

Format: 

Mnemonic: LD Operands: HL, (nn) 



LoaD 



67 



SERIES I EDITOR/ASSEMBLER 



Object Code: 










i i i 

10 

1 1 1 


1 





1 









III 

n n n n 

i i i 


n 


n 


n 


n 






1 1 l 

n n n n 

i i i 


n 


n 


n 


n 



2A 



Description: 

The contents of memory address nn are loaded into the low order portion of 
register pair HL (register L), and the contents of the next highest memory 
address (nn + 1) are loaded into the high order portion of HL (register H). The 
first n operand in the assembled object code above is the low order byte of nn. 

M cycles: 5 T states: 16(4,3,3,3,3) 4 MHz E.T.: 4.00 
Condition Bits Affected: None 

Example: 

If address 4545H contains 37H and address 4546H contains A1H, after the 
instruction 

LD HL,(4545H) 

the HL register pair will contain A137H. 



LD dd,(nn) 

Operation: dd H <](nn + 1), dd L <](nn) 

Format: 

Mnemonic: LD Operands: dd, (nn) 

Object Code: 

— I 1 1 1 1 

ED 



1 


1 


1 





1 


1 





1 















1 


d 


d 


1 





1 


1 












n 


n 


n 


n 


n 


n 


n 


n 










n 


n 


n 


n 


n 


n 


n 


n 



LoaD 



68 



16 BIT LOAD GROUP 



Description: 

The contents of address nn are loaded into the low order portion of register pair 
dd, and the contents of the next highest memory address (nn + 1) are loaded 
into the high order portion of dd. Register pair dd defines BC, DE, HL, or SP 
register pairs, assembled as follows in the object code: 

Pair dd 



BC 
DE 


00 
01 


HL 


10 


SP 


11 



The first n operand in the assembled object code above is the low order byte of 
(nn). 

M cycles: 6 T states: 20(4,4,3,3,3,3) 4 MHz E.T.: 5.00 
Condition Bits Affected: None 

Example 1: 

If Address 2130H contains 65H and address 2131M contains 78H after the 
instruction 

LD BC,(2130H) 

the BC register pair will contain 7865H. 

Example 2: 

If address FFFE contains 01H and address FFFF contains 02H, then after the 
instruction 

LD SP,(0FFFEH) 

the SP will contain 020 1H. 

LD IX, (nn) LoaD 

Operation: IX H <i(nn + 1), IX L <i(nn) 

Format: 

Mnemonic: LD Operands: IX, (nn) 



69 



SERIES i EDITOR/ASSEMBLER 



Object Code: 



1 


1 





1 


1 


1 





1 




















1 





1 


o 


1 

















n 


n 


n 


n 


n 


n 


n 


n 










n 


n 


n 


n 


n 


n 


n 


n 



DD 



2A 



Description: 

The contents of the address nn are loaded into the low order portion of Index 
Register IX, and the contents of the next highest memory address (nn + 1) are 
loaded into the high order portion of IX, The first n operand in the assembled 
object code above is the low order byte of nn. 

M cycles: 6 T states: 20(4,4,3,3,3,3) 4 MHz E.T.: 5.00 
Condition Bits Affected: None 

Example: 

If address 6066H contains 92H and address 6067H contains DAH, after the 
instruction 

LD IX,(6066H) 

the Index Register IX will contain DA92H. 



llj i Yj^nnj 



LoaD 



Operation: IY H <i(nrn- 1), IY L <i(nn) 

Format: 

Mnemonic: LD Operands: IY, (nn) 



70 



16 BIT LOAD GROUP 



Object Code: 



1 


1 


1 


1 


1 


1 





1 














1 





1 





1 











n 


n 


n 


n 


n 


n 


n 


n 






n 


n 


n 


n 


n 


n 


n 


n 



FD 



2A 



Description: 

The contents of address nn are loaded into the low order portion of Index 
Register IY, and the contents of the next highest memory address (nn + 1) are 
loaded into the high order portion of IY. The first n operand in the assembled 
object code above is the low order byte of nn. 

M cycles: 6 T states: 20(4,4,3,3,3,3) 4 MHz E.T.: 5.00 
Condition Bits Affected: None 

Example: 

If address 6666H contains 92H and address 6667H contains DAH, after the 
instruction 

LD IY,(6666H) 

the Index Register IY will contain DA92H. 



LD (nn),HL 



LoaD 



Operation: (nn + 1)<iH, (nn)<iL 

Format: 

Mnemonic: LD Operands: (nn), HL 



71 



SERIES 1 EDITO R/ASSEMBLER 



Object Code: 











1 











1 













n 


n 


n 


n 


n 


n 


n 


n 










n 


n 


n 


n 


n 


n 


n 


n 



22 



Description: 

The contents of the low order portion of register pair HL (register L) are loaded 
into memory address nn, and the contents of the high order portion of HL 
(register H) are loaded into the next highest memory address (nn + 1), The first 
n operand in the assembled object code above is the low order byte of nn. 

M cycles: 5 T states: 16(4,3,3,3,3) 4 MHz E.T.: 4.00 
Condition Bits Affected: None 

Example 1: 

If the content of register pair HL is 483 AH, after the instruction 

LD (B229H),HL 

address B229H will contain 3AH, and address B22AH will contain 48H. 

Example 2: 

If the register pair HL contains 504AH, then after the instruction 

LD (PLACE), HL 

the address PLACE will contain 4AH and address PLACE + 1 will contain 50H. 

Note: PLACE is a label which must be defined elsewhere in the program. 



LD (nn),dd 



LoaD 



Operation: (nn + 1)<idd H , (nn)0dd L 

Format: 

Mnemonic: LD Operands: (nn), dd 



72 



16 BIT LOAD GROUP 



Object 


Code: 












1 1 


1 

1 __L 





1 


1 





1 




1 


1 1 

d 

i i 


d 








1 


1 




n n 


I 1 
n 

1 _L 


n 


n 


n 


n 


n 




n n 


1 1 

n 

I I 


n 


n 


n 


n 


n 



ED 



Description: 

The low order byte of register pair dd is loaded into memory address (nn); the 
upper order byte is loaded into memory address (nn +1). Register pair dd 
defines either BC, DE, HL, or SP, assembled as follows in the object code: 



Pair 


dd 


BC 


00 


DE 


01 


HL 


10 


SP 


11 



The first n operand in the assembled object code is the low order byte of a two 
byte memory address. 

M cycles: 6 T states: 20(4,4,3,3,3,3) 4 MHz E.T.: 5.00 
Condition Bits Affected: None 

Example: 

If register pair BC contains the number 4644H, the instruction 
LD (1000H),BC 

will result in 44H in memory location 1000H, and 46H in memory 
location 100 1H. 



LD (nn)JX 

Operation: (nn + 1)0 IX H) (nn) IX L 

Format: 

Mnemonic: LD Operands: (nn), IX 



LoaD 



73 



SERIES 1 EDITOR/A SSEMBLER 



Object Code: 



1 


1 





1 


1 


1 





1 


















1 











1 















n 


n 


n 


n 


n 


n 


n 


n 












n 


n 


n 


n 


n 


n 


n 


n 



DD 



22 



Description: 

The low order byte in Index Register IX is loaded into memory address nn; the 
upper order byte is loaded into the next highest address (nn +1). The first n 
operand in the assembled object code above is the low order byte of nn. 

M cycles: 6 T states: 20(4,4,3,3,3,3) 4 MHz E.T.: 5.00 
Condition Bits Affected: None 

Example: 

If the Index Register IX contains 5A30H, after the instruction 

LD (4392H),IX 

memory location 4392H will contain number 30H and location 439.3H will 
contain 5 AH. 



LD (nn),IY 



LoaD 



Operation: (nn + 1 )<i IY H , (nn) <l IY L 

Format: 

Mnemonic: LD Operands: (nn), IY 



74 



16 BIT LOAD GROUP 



Object Code: 



1 


1 


1 


1 


1 


1 





1 














1 











1 











n 


n 


n 


n 


n 


n 


n 


n 








n 


n 


n 


n 


n 


n 


n 


n 



FD 



22 



Description: 

The low order byte in Index Register IY is loaded into memory address nn; the 
upper order byte is loaded into memory location (nn + 1). The first n operand in 
the assembled object code above is the low order byte of nn. 

M cycles: 6 T states: 20(4,4,3,3,3,3) 4 MHz E.T.: 5.00 
Condition Bits Affected: None 

Example: 

If the Index Register IY contains 4174H after the instruction 

LD 8838H,IY 

memory location 8838H will contain number 74H and memory location 8839H 
will contain 41H. 



LD SRH 



LoaD 



Operation: SP<^HL 

Format: 

Mnemonic: LD Operands: SP, HL 

Object Code: 



1 


1 


1 


1 


1 








1 



F9 



Description: 

The contents of the register pair HL are loaded into the Stack Pointer SP. 



75 



SERIES I EDITOR/ASSEMBLER 



M cycles: 1 T states: 6 4 MHz E.T. : 1 .50 
Condition Bits Affected: None 

Example: 

If the register pair HL contains 442EH, after the instruction 

LD SP.HL 

the Stack Pointer will also contain 442EH. 

LLJ Or, I A LoaD 

Operation: SP<0 IX 

Format: 

Mnemonic: LD Operands: SP, IX 

Object Code: 

__! ! ! ! ! 

DD 



F9 



Description: 

The two-byte contents of Index Register IX are loaded into the Stack Pointer SP. 
M cycles: 2 T states: 10(4,6) 4 MHz E.T.: 2.50 

Condition Bits Affected: None 

Example: 

If the contents of the Index Register IX are 98DAH, after the instruction 

LD SP.IX 

the contents of the Stack Pointer will also be 98DAH. 



1 


1 





1 


1 


1 





1 




1 


1 


1 


1 


1 








1 



76 



16 BIT LOAD GROUP 



Object Code: 










! I I 

1111 

1 1 1 


1 


1 





1 




1 1 1 
1111 


1 








1 



LD SRIY LoaD 

Operation: SP<] I Y 

Format: 

Mnemonic: LD Operands: SP, IY 



FD 



F9 



Description: 

The two byte contents of Index Register IY are loaded into the Stack Pointer SP. 
M cycles: 2 T states: 10(4,6) 4 MHz E.T.: 2.50 

Condition Bits Affected: None 

Example: 

If Index Register IY contains the integer A227H, after the instruction 

LD SP.IY 

the Stack Pointer will also contain A227H. 

PUSH qq 

Operation: (SP - 2)<i qq L , (SP - 1 )<i qq H 

Format: 

Mnemonic: PUSH Operands: qq 

Object Code: 



— I 1 1 1 1 1 | 

1 1 q q 1 1 

I I I l l 1 I 



77 



SERIES i EDITOR/ASSEMBLER 






Description: 

The contents of the register pair qq are pushed into the external memory LIFO 
(last-in, first-out) Stack. The Stack Pointer (SP) register pair holds the 16-bit 
address of the current "top" of the Stack. This instruction first decrements the 
SP and loads the high order byte of register pair qq into the memory address 
now specified by the SP, then decrements the SP again and loads the low order 
byte of qq into the memory location corresponding to this new address in the 
SP. The operand qq means register pair BC, DE, HL, or AF, assembled as 
follows in the object code: 



Pair 


qq 


BC 


00 


DE 


01 


HL 


10 


AF 


11 


M cycles: 


.3 



T states: 11(5,3,3) 4 MHz E.T.: 2.75 
Condition Bits Affected: None 

Example: 

If the AF register pair contains 2233H and the Stack Pointer contains 1007H, 
after the instruction 

PUSH AF 

memory address 1006H will contain 22H, memory address 1005H will contain 
33H, and the Stack Pointer will contain 1005H. In other words the number from 
register pair AF is now on the top of the stack, and the stack pointer is pointing 
to it. 



Before: 






Register AF 


Address 


Stack 


2233 


1007 


FF 




1008 


35 


Stack Pointer 






1007 






After: PUSH 


AF 




Register AF 


Address 


Stack 


2233 


1005 


33 




1006 


22 




1007 


FF 




1008 


35 


Stack Pointer 






1005 







78 



16 BIT LOAD GROUP 



Object Code: 










I I I 

110 1 

i i i 


1 


1 





1 




1110 

1 1 1 





1 




1 


1 



PUSH IX 

Operation: (SP - 2) IX L , (SP - 1 )<1 IX H 

Format: 

Mnemonic: PUSH Operands: IX 



DD 



E5 



Description: 

The contents of the Index Register IX are pushed into the external memory 
LIFO (last-in, first-out) Stack. The Stack Pointer (SP) register pair holds the 
16-bit address of the current "top" of the Stack. This instruction first 
decrements the SP and loads the high order byte of IX into the memory address 
now specified by the SP, then decrements the SP again and loads the low order 
byte into the memory location corresponding to this new address in the SP. 

M cycles: 3 T states: 15(4,5,3,3) 4 MHz E.T.: 3.75 
Condition Bits Affected: None 

Example: 

If the Index Register IX contains 2233H and the Stack Pointer contains 1007H, 

after the instruction 

PUSH IX 

memory address 1006H will contain 22H, memory address 1005H will contain 

33H, and the Stack Pointer will contain 1005H. The number from the IX 

register pair is now on the top of the stack. 

Before: 



Register IX 


Address 


Stack 


2233 


1007 


FF 




1008 


35 


Stack Pointer 






1007 







79 



SERIES I EDITOR/ASSEMBLER 



After: 



PUSH 



IX 



Register IX 


Address 


Stack 


2233 


1005 


33 




1006 


22 




1007 


FF 




1008 


35 


Stack Pointer 






1005 







Operation: (SP - 2)<l I Y L , (SP - 1 )<l I Y H 

Format: 

Mnemonic: PUSH Operands: IY 



Object Code: 




I I I 

1111 

i i i 


ill- 

110 1 

1 1 1 




1 1 i 

1110 

i i i 


1 1 1 
10 1 

1 1 1 



FD 



E5 



Description: 

The contents of the Index Register IY are pushed into the external memory 
UFO (last-in, first-out) Stack. The Stack Pointer (SP) register pair holds the 
16-bit address of the current "top" of the Stack. This instruction first 
decrements the SP and loads the high order byte of IY into the memory address 
now specified by the SP; then decrements the SP again and loads the low order 
byte into the memory location corresponding to this new address in the SP. 

M cycles: 4 T states: 15(4,5,3,3) 4 MHz E.T.: 3.75 
Condition Bits Affected: None 

Example: 

If the Index Register IY contains 22.33H and the Stack Pointer contains 1007H, 
after the instruction 

PUSH IY 



80 



^^tmmm^umK^mmm^^^i^^^^^^^^ ^^i^mf ^^^^^^^^ ^^^^^^^^^^^^^^^ ^^^ 



memory address 1006H will contain 22H, memory address 1005 H will contain 
33H, and the Stack Pointer will contain 1005H. The number from register pair 
IY is now on the top of the stack. 

Before: 

Register IY Address Stack 

2233 1007 FF 

1008 35 

Stack Pointer 
1007 

After: PUSH IY 



Register IY 


Address 


Stack 


2233 


1005 


33 




1006 


22 




1007 


FF 




1008 


35 


Stack Pointer 






1005 







Operation: qq H <i(SP + 1), qq L 0(SP) 

Format: 

Mnemonic: POP Operands: qq 



Object Code: 

— ] ( ! , , , , 

1 1 q q 1 

i ill I I I 



Description: 

The top two bytes of the external memory LIFO (last-in, first-out) Stack are 
popped into register pair qq. The Stack Pointer (SP) register pair holds the 16-bit 
address of the current "top" of the Stack. This instruction first loads into the 
low order portion of qq, the byte at the memory location corresponding to the 
contents of SP; then SP is incremented and the contents of the corresponding 
adjacent memory location are loaded into the high order portion of qq and the 
SP is now incremented again. The operand qq defines register pair BC, DE, HL, 
or AF, assembled as follows in the object code: 



81 



SERIES I EDITOR/ASSEMBLER 



Pair 


r 


BC 


00 


DE 


01 


HL 


10 


AF 


11 



M cycles: 3 T states: 10(4,3,3) 
Condition Bits Affected: None 



4MHzE.T.:2.50 



Example: 

If the Stack Pointer contains 1000H, memory location 1000H contains 55H, and 
location 1001H contains 33H, the instruction 

POP HL 

will result in register pair HL containing 3355H, and the Stack Pointer 
containing 1002H. In other words register pair HL contains the number which 
was on the top of the stack, and the stack pointer is pointing to the current top of 
the stack. 

Before: 



Register HL 


Address 


Stack 


2233 


1000 


55 




1001 


33 




1002 


A4 




1003 


62 


Stack Pointer 






1000 






After: POP 


HL 




Register HL 


Address 


Stack 


3355 


1002 


A4 




1003 


62 


Stack Pointer 






1002 







POP IX 

Operation: IX H 0(SP + 1), IX L <l(SP) 

Format: 

Mnemonic: POP Operands: IX 



sis 
82 



Object Code: 



16 BIT LOAD GROUP 



1 


1 





1 


1 


1 





1 




1 


1 


1 














1 



DD 



El 



Description: 

The top two bytes of the external memory LIFO (last-in, first-out) Stack are 
popped into Index Register IX. The Stack Pointer (SP) register pair holds the 
16-bit address of the current "top" of the Stack. This instruction first loads into 
the low order portion of IX the byte at the memory location corresponding to the 
contents of SP; then SP is incremented and the contents of the corresponding 
adjacent memory location are loaded into the high order portion of IX. The SP 
is now incremented again. 

M cycles: 4 T states: 14(4,4,3,3) 4 MHzE.T.: 3.50 



Condition Bits Affected: None 

Example: 

If the Stack Pointer contains 1000H, memory location 1000H contains 55H, and 
location 1001H contains 33H, the instruction 

POP IX 

will result in the Index Register IX containing 3355H, and the Stack Pointer 
containing 1002H. Register pair IX contains the number which used to be on the 
top of the stack. 

Before: 



Register IX 

24F9 



Address 

1000 
1001 
1002 
1003 



Stack 

55 
33 
A4 
62 



Stack Pointer 

1000 



83 



SERIES I EDITOR /ASSEMBLER 



After: POP 


IX 




Register IX 


Address 


Stack 


3355 


1002 


A4 




1003 


62 


Stack Pointer 






1002 







POP 1Y 



Operation: IY H <](SP + 1),IY L <l(SP) 

Format: 

Mnemonic: POP Operands: IY 

Object Code: 



1 


1 


1 


1 


1 


1 





1 




1 


1 


1 














1 



FD 



El 



Description: 

The top two bytes of the external memory LIFO (last-in, first-out) Stack are 
popped into Index Register IY. The Stack Pointer (SP) register pair holds the 
16-bit address of the current "top" of the Stack. This instruction first loads into 
the low order portion of IY the byte at the memory location corresponding to the 
contents of SP; then SP is incremented and the contents of the corresponding 
adjacent memory location are loaded into the high order portion of IY. The SP 
is now incremented again. 

M cycles: 4 T states: 14(4,4,3,3) 4 MHz E.T.: 3.50 
Condition Bits Affected: None 

Example: 

If the Stack Pointer contains 1000H, memory location 1000H contains 55H, and 
location 1001H contains 33H, the instruction 

POP IY 

will result in Index Register IY containing 3355H, and the Stack Pointer 
containing 1002H. Register pair IY contains the number which used to be on the 
top of the stack. 



84 



18 BIT LOAD GROUP 

mmmmmimmmmmmm>imtMmmmmmtmm 



Before: 



Register IY 


Address 


Stack 


24F9 


1000 


55 




1001 


33 




1002 


A4 




1003 


62 


Stack Pointer 






1000 






After: POP 


IY 




Register IY 


Address 


Stack 


3355 


1002 


A4 




1003 


62 


Stack Pointer 






1002 







85 



EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP 



Exchange, Block Transfer 
and Search Group 

EX DE,HL Exchange 

Operation: DE<][>HL 



Format: 

Mnemonic: EX Operands: DE, HL 

Object Code: 

— I 1 1 | | 

EB 



! j ! j j , , 

1110 10 11 

i i l l I I I — 



Description: 

The two-byte contents of register pairs DE and HL are exchanged. 
M cycles: 1 T states: 4 4 MHz E.T.: 1.00 

Condition Bits Affected: None 

Example: 

If the content of register pair DE is the number 2822H, and the content of the 
register pair HL is number 499AH, after the instruction 

EX DE,HL 

the content of register pair DE will be 499AH and the content of register pair 

HL will be 2822H. 

EXAFjAP Exchange 

Operation: AF<H>AF' 

Format: 

Mnemonic: EX Operands: AF, AF' 



87 



SERIES i EDITOR/ASSEI 



Object Code: 



— I 1 I I I I I 

10 

I I I I I I I 



Description: 

The two-byte contents of the register pairs AF and AF' are exchanged. 
(Note: register pair AF' consists of registers A' and F.') 

M cycles: 1 T states: 4 4 MHz E.T.: 1.00 
Condition Bits Affected: None 

Example: 

If the content of register pair AF is number 9900H, and the content of register 
pair AF' is number 5944H, after the instruction 

EX AF,AF' 

the contents of AF will be 5944H, and the contents of AF will be 9900H. 



Exchange 

Operation: (BC)<H>(BC), (DE)<ft>(DE'), (HL)<H>(HL') 

Format: 

Mnemonic: EXX Operands: 

Object Code: 

I I I I | 

D9 



1 I I I I I I 
10 1 10 1 

J I I I ! I I 



Description: 

Each two-byte value in register pairs BC, DE, and HL is exchanged with the 
two-byte value in BC,' DE,' and HL,' respectively. 

M cycles: 1 T states: 4 4 MHz E.T.: 1.00 
Condition Bits Affected: None 

Example 1: 

If the contents of register pairs BC, DE, and HL are the numbers 445AH, 
3DA2H, and 8859H, respectively, and the contents of register pairs BC,' DE,' 
and HL' are 0988H, 9300H, and 00E7H, respectively, after the instruction 



88 



EXCHAN GE, BLOCK TRANSFER AND SEARCH GROUP 



EXX 

the contents of the register pairs will be as follows: BC: 0988H; DE: 9300H; 

HL: 00E7H; BC: 445AH; DE': 3DA2H; and HL': 8859H. 



Example 2: 

If the contents of the registers are as shown: 



BC 


111 1H 


DE 


2222H 


HL 


3333H 


BC 


4444H 


DE' 


5555H 


HL' 


6666H 


Then after 


an EXX ir 


BC 


4444H 


DE 


5555H 


HL 


6666H 


BC 


1111H 


DE' 


2222H 


HL' 


3333H 



Exchange 



Operation: H <K> (SP + 1), L<][>(SP) 

Format: 

Mnemonic: EX Operands: (SP),HL 



Object Code: 



— I 1 1 1 1 1 1 

1110 11 

_J I I I I I I 



E3 



Description: 

The low order byte contained in register pair HL is exchanged with the contents 
of the memory address specified by the contents of register pair SP (Stack 
Pointer), and the high order byte of HL is exchanged with the next highest 
memory address (SP+ 1). 

M cycles: 5 T states: 19(4,3,4,3,5) .4 MHz E.T.: 4.75 
Condition Bits Affected: None 



89 



SERIES I EDITOR/ASSEMBLER 



Example: 

If the HL register pair contains 7012H, the SP register pair contains 8856H, the 
memory location 8856H contains the byte 1 1H, and the memory location 8857H 
contains the byte 22H, then the instruction 

EX (SP),HL 

will result in the HL register pair containing number 221 1H, memory location 
8856H containing the byte 12H, the memory location 8857H containing the byte 
70H and the Stack Pointer containing 8856H. 



Before: 



Register HL 


Address 


Stack 


7012 


8856 


11 




8857 


22 




8858 




Stack Pointer 






8856 






After: 






Register HL 


Address 


Stack 


2211 


8856 


12 




8857 


70 




8858 




Stack Pointer 






8856 







EX(SP),IX 



Operation: IX H <X> (SP + 1), IX L <H>(SP) 

Format: 

Mnemonic: EX Operands: (SP), IX 

Object Code: 

I I I 1 1 

DD 



E3 



1 


1 





1 


1 


1 





1 




1 


1 


1 











1 


1 



Exchange 



90 



EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP 



Description: 

The low order byte in Index Register IX is exchanged with the contents of the 
memory address specified by the contents of register pair SP (Stack Pointer), 
and the high order byte of IX is exchanged with the next highest memory 
address (SP + 1). 

Condition Bits Affected: None 

Example: 

If the Index Register IX contains 3988H, the SP register pair contains 0100H, 
the memory location 0100H contains the byte 90H, and memory location 0101H 
contains byte 48H, then the instruction 

EX (SP),IX 

will result in the IX register pair containing number 4890H, memory location 
0100H containing 88H, memory location 0101H containing 39H and the Stack 
Pointer containing 0100H. 



Address 

0100 
0101 



Before: 

Register IX 

3988 

Stack Pointer 

0100 

After: 

Register IX Address 

4890 

Stack Pointer 

0100 



0100 
0101 



Stack 

90 

48 



Stack 

88 
39 



EX(SP),IY 

Operation: IY H «>(SP + 1), IY L <H>(SP) 

Format: 

Mnemonic: EX Operands: (SP), IY 



Exchange 



91 



SERIES I EDITOR/ASSEMBLER 



Object Code: 



1 


1 


1 


1 


1 


1 





1 




1 


1 


1 











1 


1 



FD 



E3 



Description: 

The low order byte in Index Register IY is exchanged with the contents of the 
memory address specified by the contents of register pair SP (Stack Pointer), 
and the high order byte of IY is exchanged with the next highest memory 
address (SP+1). 

M cycles: 6 T states: 23(4,4,3,4,3,5) 4 MHz E.T.: 5.75 
Condition Bits Affected: None 

Example: 

If the Index Register IY contains 3988H, the SP register pair contains 0100H, 
the memory location 0100H contains the byte 90H, and memory location 
0101H contains byte 48H, then the instruction 

EX (SP),IY 

will result in the IY register pair containing number 4890H, memory location 
0100H containing 88H, memory location 0101H containing 39H, and the Stack 
Pointer containing 0100H. 

Before: 



Register IY 


Address 


Stac 


3988 


0100 


90 




0101 


48 


Stack Pointer 






0100 







After: 

Register IY 

4890 

Stack Pointer 

0100 



Address 

0100 
0101 



Stack 



39 



92 



EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP 



LDI LoaD & Increment 

Operation: (DE) <i (HL), DE DE + 1 , HL_0 HL + 1 , BC <i BC - 1 



Format: 

Mnemonic: LDI Operands: 



Object Code: 










I I I 
1110 

i i i 


1 


1 





1 




1 1 l 
10 10 

1 1 1 















ED 



AO 



Description: 

A byte of data is transferred from the memory location addressed by the 
contents of the HL register pair to the memory location addressed by the 
contents of the DE register pair. Then both these register pairs are incremented 
and the BC (Byte Counter) register pair is decremented. 

M cycles: 4 T states: 16(4,4,3,5) 4 MHz E.T.: 4.00 

Condition Bits Affected: 

S: Not affected 

Z: Not affected 

H: Reset 

P/ V : Set if BC - 1 =/= 0; reset otherwise 

N: Reset 

C: Not affected 

Example 1: 

If the HL register pair contains 1 1 1 1H, memory location 1 1 1 1H contains the byte 
88H, the DE register pair contains 2222H, the memory location 2222H contains 
byte 66H, and the BC register pair contains 7H, then the instruction 

LDI 

will result in the following contents in register pairs and memory addresses: 



HL 


1112H 


(111 1H) 


88H 


DE 


2223H 


(2222H) 


88H 


BC 


6H 



93 



SERIES I EDITOR/ASSEMBLER 



and the condition Bits will be: 



1 



S Z H P/V N C 

Example 2: 

If the contents of registers and memory are as shown: 



HL 


7C00H 


(7C00) 


FFH 


DE 


3C00H 


(3C00) 


00H 


BC 


1H 


Then after 


an LDI instruction the registers and memory will contain the 


following: 




HL 


7C01H 


(7C00) 


FFH 


DE 


3C01H 


(3C00) 


FFH 


BC 


3H 



and the condition bits will be: 







S Z H P/V N C 



Example 3: 

The following program will move 80 consecutive bytes from BUF1 to BUF2: 
HL, BUF1 



LD 
LD 
LD 



DE, BUF2 
BC, 80 

LOOP LDI 

JP NZ, LOOP 



LDIR 



LoaD Increment & Repeat 



Operation: (DE)O(HL), DE<]DE + 1, HL<iHLH- 1, BCOBC- 1 

Format: 

Mnemonic: LDIR Operands: 



94 



EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP 



Object Code: 






1110 

i i i 


1 


1 1 

1 1 




10 11 

1 1 1 





1 1 


1 1 



ED 



B0 



Description: 

This two-byte instruction transfers a byte of data from the memory location 
addressed by the contents of the HL register pair to the memory location 
addressed by the DE register pair. Then both these register pairs are incremented 
and the BC (Byte Counter) register pair is decremented. If decrementing causes 
the BC to go to zero, the instruction is terminated. If BC is not zero the program 
counter (PC) is decremented by 2 and the instruction is repeated. Note that if 
BC is set to zero prior to instruction execution, the instruction will loop through 
64K bytes. Also, interrupts will be recognized after each data transfer. 

ForBC^O: 

4MHzE.T.:5.25 



4MHzE.T.:4i 



M cycles 


5 T states: 


21(4,4,3,5,5) 


For BC = 


0: 




M cycles 


4 T states: 


16(4,4,3,5) 


Condition Bits Affected 




S: 
Z: 


Not affected 
Not affected 




H: 


Reset 




P/V: 


Reset 




N: 


Reset 




C: 


Not affected 





Example: 

If the HL register pair contains 111 1H, the DE register pair contains 2222H, the 
BC register pair contains 0003H, and memory locations have these contents: 



(111 1H) 

(1112H) 
(1113H) 



88H 
36H 
A5H 



(2222H) 
(2223H) 
(2224H) 



66H 
59H 
C5H 



then after the execution of 
LDIR 



95 



SERIES i EDITOR/ASSEMBLER 



Hni— WMia— a 



wmmmmmmMmmmmiimmmmmmmmmmmmSM^^iii^iuuuMiM^fiMaitiKiit 



the contents of register pairs and memory locations will be: 



HL 


1114H 






DE 


2225H 






BC 


0000H 






(111 1H) 


88H 


(2222H) 


88H 


(1112H) 


36H 


(2223H) 


36H 


(1113H) 


A5H 


(2224H) 


A5H 



and the H, P/V, and N flags are all zero. 



ULJ LoaD Decrement 

Operation: (DE)0(HL),DE<iDE~-1,HL<]HL-1,BC<]BC-1 



Format: 

Mnemonic: LDD Operands: 



Object Code 


• 










I I 
1 1 1 

i i 




1 


1 


1 





1 




I I 
1 1 





1 












ED 



A8 



Description: 

This two-byte instruction transfers a byte of data from the memory location 
addressed by the contents of the HL register pair to the memory location 
addressed by the contents of the DE register pair. Then both of these register 
pairs, including the BC (Byte Counter) register pair, are decremented. 



M cycles 


4 T states: 


16(4,4,3,5) 


4 MHz E.T. 


4 


Condition Bits Affected 








S: 
Z: 
H: 

P/V: 

N: 

C: 


Not affected 

Not affected 

Reset 

Set if BC - 1 * 0; reset other 

Reset 

Not affected 


wise 





96 



EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP 



Example 1: 

If the HL register pair contains 111 1H, memory location 111 1H contains the byte 
88H, the DE register pair contains 2222H, memory location 2222H contains 
byte 66H, and the BC register pair contains 7H, then the instruction 

LDD 

will result in the following contents in register pairs and memory addresses: 

HL : 1110H 

(1111H) : 88H 

DE : 222 1H 

(2222H) : 88H 

BC : 6H 

and the condition bits will be: 



1 



S Z H P/V N C 

Example 2: 

If the contents of registers and memory are as shown: 



HL 


7CFFH 


(7CFF) 


3CH 


DE 


3CFFH 


(3CFF) 


00H 


BC 


1H 


Then after 


a LDD instruction the registers and memory will contain the 


following: 




HL 


7CFEH 


(7CFF) 


3CH 


DE 


3CFEH 


(3CFF) 


. 3CH 


BC 


: 0H 



and the condition bits will be: 



I I I 



S Z H P/V N C 



DDR LoaD Decrement & Repeat 

Operation: (DE) <j (HL), DE <i DE - 1 , HL<] HL - 1 , BC <i BC - 1 



Format: 
Mnemonic: LDDR 



Operands: 



97 



SERIES i EDITOR/ASSEMBLER 



Object Co 


tie: 




1 1 

1 1 

i i 


1 1 



.. i ) 


1 1 1 

1 1 

1 1 1 




1 1 
1 

1 1 


l l 
1 

l 1 


1 1 1 


1 1 1 



ED 



B8 



Description: 

This two-byte instruction transfers a byte of data from the memory location 
addressed by the contents of the HL register pair to the memory location 
addressed by the contents of the DE register pair. Then both of these registers 
as well as the BC (Byte Counter) are decremented. If decrementing causes the 
BC to go to zero, the instruction is terminated, If BC is not zero, the program 
counter (PC) is decremented by 2 and the instruction is repeated. Note that if 
BC is set to zero prior to instruction execution, the instruction will loop through 
64K bytes. Also, interrupts will be recognized after each data transfer. 

For BC^0: 



M cycles: 5 
ForBC = 0: 

M cycles: 4 



T states: 21(4,4,3,5,5) 4 MHz E.T.: 5.25 



T states: 16(4,4,3,5) 



4MHzE.T:4. 



Condition Bits Affected: 



S: 

Z: 

H: 

P/V: 

N: 

C: 



Not affected 

Not affected 

Reset 

Reset 

Reset 

Not affected 



Example: 

If the HL register pair contains 1 1 14H, the DE register pair contains 2225H, the 
BC register pair contains 0003H, and memory locations have these contents: 



(1114H) 


A5H 


(2225H) 


C5H 


(1113H) 


36H 


(2224H) 


59H 


(1112H) 


88H 


(2223H) 


66H 



then after the execution of 
LDDR 



EZj 
98 



mm 



EXCHANGE, BLOCK TRANSFER AND SEARC8 

K3agBe3a»H«a^ ^ .^».»«^*..*».'^^^...»^- ' ;.«^f: :.'c<, • r •&„-;„; „Z 3 



the contents of register pairs and memory locations will be: 



HL 
DE 
BC 

(1114H) 
(1113H) 
(1112H) 



1111H 

2222H 
0000H 

A5H 
36H 
88H 



(2225H) 

(2224H) 
(2223H) 



A5H 
36H 
88H 



and the H, P/V, and N flags are all zero. 



CP1 ComPare & Increment 

Operation: A -(HL), HL<lHL+1, BC<lBC- 1 



Format: 

Mnemonic: CPI Operands: 



Object Code: 








I I I 
1110 

i i i 


1 


1 


1 
1 

1 




1 1 I 
10 10 

1 1 1 








1 
1 

1 



ED 



Al 



Description: 

The contents of the memory location addressed by the HL register pair is 
compared with the contents of the Accumulator. In case of a true compare, the 
Z condition bit is set. Then HL is incremented and the Byte Counter (register 
pair BC) is decremented. 

M cycles: 4 T states: 16(4,4,3,5) 4 MHz E.T.: 4.00 

Condition Bits Affected: 

S: Set if result is negative; reset otherwise 

Z: Set if A = (HL); reset otherwise 

H: Set if borrow from Bit 4; reset otherwise 

P/V: Reset if BC becomes 0; set otherwise 

N: Set 

C: Not affected 



99 



SERIES I EDITOR/ASSEMBLER 



Example: 

If the HL register pair contains 111 1H, memory location 111 1H contains 3BH, 
the Accumulator contains 3BH, and the Byte Counter contains 000 1H, then after 
the execution of 

CP1 

the Byte Counter will contain 0000H, the HL register pair will contain 1 1 12H, 

the Z flag in the F register will be set, and the P/V flag in the F register will be 

reset. There will be no effect on the contents of the Accumulator or address 

1111H. 

If the contents of memory and registers are as shown 



HL 


8A00H 


(8A00H) 


6DH 


A 


75H 


BC 


5H 



Then during the execution of a CPI instruction the Arithmetic and Logic Unit 
will do the following subtraction: 



Borrow needed here 



75H = 0111 
-6DH = 0110 



o 

0101 
1101 



8H = 0000 H 
After CPI is executed registers and memory will contain the following 



HL 


8A01H 


(8A00H) 


6DH 


A 


75H 


BC 


4H 



and the condition bits would be: 









1 1 1 


1 





S 


Z 


H P/V N 


C 


result positive 


o 


■o 


o o o 


o not affected 


match not found 








always set 


borrow from bit 4 








BC not zero 


Example 3: 











The following program is used to verify that the contents of two 80-byte buffers 
are identical. Each time a mismatch is found the program calls a subroutine 
called ERROR. 



100 



STRT 



LOOP 



END 



EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP 



LD 


HL, BUF1 


LD 


DE, BUF2 


LD 


BC, 80 


LD 


A, (DE) 


CPI 




CALL 


NZ, ERROR 


INC 


DE 


JR 


PO, LOOP 



CDID 
rlri 



ComPare Increment & Repeat 



Operation:A-(HL),HL<lHL+1,BC<lBC-1 



Format: 

Mnemonic: CPIR Operands: 

Object Code: 



1 


1 


1 





1 


1 





1 




1 





1 


1 











1 



ED 



Bl 



Description: 

The contents of the memory location addressed by the HL register pair is 

compared with the contents of the Accumulator. In case of a true compare, the 

Z condition bit is set. The HL is incremented and the Byte Counter (register 

pair BC) is decremented. If decrementing causes the BC to go to zero or if 

A = (HL), the instruction is terminated. If BC is not zero and A ¥= (HL), the 

program counter is decremented by 2 and the instruction is repeated. Note that if 

BC is set to zero before the execution, the instruction will loop through 64K 

bytes, if no match is found. Also, interrupts will be recognized after each data 

comparison. 

ForBC^QandA^(HL): 

M cycles: 5 T states: 21(4,4,3,5,5) 4 MHz E.T.: 5.25 

ForBC^0orA = (HL): 

M cycles: 4 T states: 16(4,4,3,5) 4 MHz E.T.: 4.00 



101 



SERIES 1 EDITOR/ASSEMBLER 



Condition Bits Affected: 

S: Set if result is negative; reset otherwise 

Z: Set if A = (HL); reset otherwise 

H: Set if borrow from Bit 4; reset otherwise 

P/V: Reset if BC becomes 0; set otherwise 

N: Set 

C: Not affected 

Example: 

If the HL register pair contains 1 1 1 1H, the Accumulator (Register A) contains 
F3H, the Byte Counter contains 0007H, and memory locations have these 
contents: 



(1111H) 
(1112H) 
(1113H) 



52H 
00H 
F3H 



then after the execution of 

CPIR 

the contents of register pair HL will be 1 1 14H, and the contents of the Byte 
Counter will be 0004H. Since BC^0, the P/V flag is still set. This means that it 
did not search through the whole block before the instruction stopped. Since a 
match was found, the Z flag is set. 

The following program uses the CPIR instruction to count the number of nulls 
(00H) found in an 80-byte buffer. The count is kept in register E. 



STRT 


LD 


BC, 80 




LD 


HL, BUFF 




LD 


A, 




LD 


E, 


LOOP 


CPIR 






JR 


NZ, FOO 




INC 


E 


FOO 


JP 


PE, LOOP 



CPD 



Com Pare & Decrement 

Operation: A -(HL), HL<lHL- 1, BC<lBC- 1 

Format: 

Mnemonic: CPD Operands: 

102 



EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP 



Object Code: 








1 ! 1 

1110 

i I I 


1 


1 


1 

1 

1 




1 1 1 

10 10 

1 1 1 


1 





1 
1 

1 



ED 



A9 



Description: 

The contents of the memory location addressed by the HL register pair is 
compared with the contents of the Accumulator. In case of a true compare, the Z 
condition bit is set. The HL and the Byte Counter (register pair BC) are 
decremented. 

M cycles: 4 T states: 16(4,4,3,5) 4 MHz E.T.: 4.00 

Condition Bits Affected: 

S: Set if result is negative; reset otherwise 

Z: Set if A = (HL); reset otherwise 

H: Set if borrow from Bit 4; reset otherwise 

P/V: Reset if BC becomes zero; set otherwise 

N: Set 

C: Not affected 

Example: 

If the HL register pair contains 1 1 1 1H, memory location 1 1 1 1H contains 3BH, 
the Accumulator contains 3BH, and the Byte Counter contains 000 1H, then after 
the execution of 

CPD 

the Byte Counter will contain 0000H, the HL register pair will contain 1 1 10H, 
the Z flag in the F register will be set and the P/V flag in the F register will be 
reset. There will be no effect on the contents of the Accumulator or address 
1111H. 

Since the CPD instruction decrements HL, it is used to search through memory 
from high to low addresses. Otherwise it is similar to the CPI instruction. 

V U H Com Pare Decrement & Repeat 

Operation: A -(HL), HL<lHL- 1, BC<lBC- 1 

Format: 

Mnemonic: CPDR Operands: 



103 



SERIES I EDITOR/ASSEMBLER 



Object Code: 



1 


1 


1 





1 


1 





1 




1 





1 


1 


1 








1 



ED 



B9 



Description: 

The contents of the memory location addressed by the HL register pair is 
compared with the contents of the Accumulator. In case of a true compare, the 
Z condition bit is set. The HL and BC (Byte Counter) register pairs are 
decremented. If decrementing causes the BC to go to zero or if A = (HL), the 
instruction is terminated. If BC is not zero and A=£ (HL), the program counter is 
decremented by 2 and the instruction is repeated. Note that if BC is set to zero 
prior to instruction execution, the instruction will loop through 64K bytes, if no 
match is found. Also, interrupts will be recognized after each data comparison. 

ForBC#0andA*(HL): 

M cycles: 5 T states: 21(4,4,3,5,5) 4 MHz E.T.: 5.25 

For BC = or A = (HL): 

M cycles: 4 T states: 16(4,4,3,5) 4 MHz E.T.: 4.00 



Condition Bits Affected: 

S: Set if result is negative; reset otherwise 

Z: Set if A = (HL), reset otherwise 

H: Set if borrow from Bit 4; reset otherwise 

P/V: Reset if BC becomes zero; set otherwise 

N: Set 

C: Not affected 



Example: 

If the HL register pair contains 1 1 18H, the Accumulator contains F3H, the Byte 
Counter contains 0003H, and memory locations have these contents: 



(1118H) 
(1117H) 
(1116H) 



52H 
00H 
F3H 



then after the execution of 

CPDR 

the contents of register pair HL will be 1115H, the contents of the Byte Counter 

will be 0000H, the P/V flag in the F register will be reset, and the Z flag in the 

F register will be set. 



104 



8 BIT ARITHMETIC AMD LOGICAL GROUP 



it Arithmetic and Logical Group 



5" 

Operation: A (} A + X 

Format: 

Mnemonic: ADD Operands: A, r 

Object Code: 



1 














r 


1 
r r 

1 



Description: 

The contents of register r are added to the contents of the Accumulator, and the 
result is stored in the Accumulator. The symbol r identifies the registers A, B, 
C, D, E, H or L assembled as follows in the object code: 

Register r 

A = 111 

B = 000 

C = 001 

D = 010 

E = 011 

H = 100 

L = 101 

M cycles: 1 T states: 4 4 MHz EX: 1.00 

Condition Bits Affected: 

S: Set if result is negative; reset otherwise 

Z: Set if result is zero; reset otherwise 

H: Set if carry from Bit 3; reset otherwise 

P/V: Set if overflow; reset otherwise 

N: Reset 

C: Set if carry from Bit 7; reset otherwise 

Example: 

If the contents of the Accumulator are 44H, and the contents of register C are 
11H, after the execution of 

ADD A,C 



105 



SERIES 1 EDITOR/ASSEMBLER 



the contents of the Accumulator will be 55H. See Appendix K for more details 
of condition bits affected. 



ADD A ? n 

Operation: A (lA + n 

Format: 

Mnemonic: ADD Operands: A, n 

Object Code: 



1 


1 











1 


1 







n 


n 


n 


n 


n 


n 


n 


n 



C6 



Description: 

The integer n is added to the contents of the Accumulator and the results are 
stored in the Accumulator. 

M cycles: 2 T states: 7(4,3) 4 MHz E.T.: 1.75 

Condition Bits Affected: 

S: Set if result is negative; reset otherwise 

Z: Set if result is zero; reset otherwise 

H: Set if carry from Bit 3; reset otherwise 

P/V: Set if overflow; reset otherwise 

N: Reset 

C: Set if carry from Bit 7; reset otherwise 

Example: 

If the contents of the Accumulator are 23H, after the execution of 

ADD A,33H 

the contents of the Accumulator will be 56H. 



106 



I ^ik.:^g | 's.y '. : .•v.r.Tfg! 



8 BIT ARITHMETI C AND LOGICAL GROUP 



Operation: A(l A+ (HL) 

Format: 

Mnemonic: ADD Operands: A, (HL) 



Object Code: 



1 














1 


1 






86 



Description: 

The byte at the memory address specified by the contents of the HL register 
pair is added to the contents of the Accumulator and the result is stored in the 
Accumulator. 

M cycles: 2 T states: 7(4,3) 4 MHz E.T.: 1.75 

Condition Bits Affected: 

S: Set if result is negative; reset otherwise 

Z 

H 



Set if result is zero; reset otherwise 

Set if carry from Bit 3; reset otherwise 
P/V: Set if overflow; reset otherwise 

N: Reset 

C: Set if carry from Bit 7; reset otherwise 

Example: 

If the contents of the Accumulator are A0H, and the content of the register 

pair HL is 2323H, and memory location 2323H contains byte 08H, after the 

execution of 

ADD A,(HL) 

the Accumulator will contain A8H. 

ADDA,(IX+d) 

Operation: A <1 A + (IX+ d) 

Format: 

Mnemonic: ADD Operands: A, (IX+d) 



107 



SERIES 1 EDITOR/ASSEMBLER 



Object Code: 



1 


1 





1 


1 


1 





1 








1 














1 


1 











d 


d 


d 


d 


d 


d 


d 


d 



DD 



86 



Description: 

The contents of the Index Register (register pair IX) is added to a two's 
complement displacement d to point to an address in memory. The contents of 
this address is then added to the contents of the Accumulator and the result is 
stored in the Accumulator. 

M cycles: 5 T states: 19(4,4,3,5,3) 4 MHz E.T.: 4.75 

Condition Bits Affected: 

S: Set if result is negative; reset otherwise 

Z: Set if result is zero; reset otherwise 

H: Set if carry from Bit 3; reset otherwise 

P/V: Set if overflow; reset otherwise 

N: Reset 

C: Set if carry from Bit 7; reset otherwise 



Example: 

If the Accumulator contents are 1 1H, the Index Register IX contains 1000H, and 
if the content of memory location 1005H is 22H, after the execution of 

ADD A,(IX+5H) 

the contents of the Accumulator will be 33H. 



ADDA,(IY+d) 

Operation: A<lA+(IY+d) 

Format: 

Mnemonic: ADD Operands: A, (IY+d) 



108 



8 BIT ARI THMETIC AND LOGICAL GROUP 



Object Code: 












1 1 I 

1 1 1 

i i i 


1 


1 


1 





1 




I 1 1 

1 

i i i 








1 


1 







1 1 1 

d d d 

i i i 


d 


d 


d 


d 


d 



FD 



Description: 

The contents of the Index Register (register pair IY) is added to the 
displacement d to point to an address in memory. The contents of this address 
is then added to the contents of the Accumulator and the result is stored in the 
Accumulator. 

M cycles: 5 T states: 19(4,4,3,5,3) 4 MHz E.T.: 4.75 

Condition Bits Affected: 

S: Set if result is negative; reset otherwise 

Z: Set if result is zero; reset otherwise 

H: Set if carry from Bit 3; reset otherwise 

P/V: Set if overflow; reset otherwise 

N: Reset 

C: Set if carry from Bit 7; reset otherwise 

Example: 

If the Accumulator contents are 1 1H, the Index Register pair IY contains 1000H, 
and if the content of memory location 1005H is 22H, after the execution of 

ADD A,(IY+5H) 

the contents of the Accumulator will be 33H. 



AOL/ A 3 
Operation: A <1 A + S + CY 



ADd with Carry 



Format: 
Mnemonic: ADC 



Operands: A, s 



The s operand is any of r, n, (HL), (IX+d) or (lY+d) as defined for the 
analogous ADD instruction. These various possible opcode-operand 
combinations are assembled as follows in the object code: 



109 



SERIES i EDITOR/ASSEMBLER 

2L_ -J 



I^^M^^g^^^M^^— ^— S 



; ; i 



Object Code: 
ADC A, r 

ADC A, n 



ADC A, (HL) 
ADC A, (IX+d) 



ADC A, (IY+d) 



1 1 1 1 1 1 1 

1 1 r r r 

I i i i i I i 




110 1110 

1 1 1 1 1 1 1 




1 1 1 1 1 1 1 

nnnnnnnn 

i i i i i i i 




1 1 1 1 1 l l 
10 1 1 10 

1 1 1 1 1 1 1 




1 1 1 1 1 1 1 
110 1110 1 

1 1 1 1 1 I 1 




1 1 1 1 1 1 1 

10 1 1 10 

1 1 1 1 1 1 1 




1 1 1 1 1 1 1 

dddddddd 

i i i i i i i 




1111110 1 

i i i i i i i 




1 1 1 1 l l l 

10 1 1 10 

I 1 1 1 1 1 1 




1 1 1 1 1 1 1 
dddddddd 

1 1 1 l l l l 



CE 



8E 



DD 



8E 



FD 



8E 



r identifies registers A, B, C, D, E, H, or L assembled as follows in the object 
code field above: 



Register 


r 


A = 


111 


B 


000 


C 


001 


D = 


010 


E = 


011 


H = 


100 


L 


101 


Description: 





The s operand, along with the Carry Flag ("C" in the F register) is added to the 
contents of the Accumulator, and the result is stored in the Accumulator. 



wmmmmmmMmssaammmmmtmimmmm 
110 



8 BIT ARITHMETIC AND LOGICAL GROUP 



M 4 MHz 

Instruction Cycles T States E.T. in (xs 

ADC A, r 14 1.00 

ADC A, n 2 7(4,3) 1-75 

ADC A, (HL) 2 7(4,3) 1.75 

ADC A, (IX+d) 5 19(4,4,3,5,3) 4.75 

ADC A, (IY+d) 5 19(4,4,3,5,3) 4.75 

Condition Bits Affected: 

S: Set if result is negative; reset otherwise 

Zi Set if result is zero; reset otherwise 

H: Set if carry from Bit 3; reset otherwise 

P/V: Set if overflow; reset otherwise 

N: Reset 

C: Set if carry from Bit 7; reset otherwise 

Example 1: 

If the Carry Flag is set, the Accumulator contains 16H, the HL register pair 
contains 6666H, and address 6666H contains 10H, after the execution of 

ADC A, (HL) 

the Accumulator will contain 27H. 

Example 2: 

If the Carry Flag is set, the Accumulator contains 30H, and register C contains 
5H, then after the execution of 

ADC A, C 

the Accumulator will contain 36H. 



SUB S SUBtract 

Operation: A <lA-S 

Format: 

Mnemonic: SUB Operands: s 

The s operand is any of r, n, (HL), (IX+ d) or (IY+ d) as defined for the 
analogous ADD instruction. These various possible opcode-operand 
combinations are assembled as follows in the object code: 



111 



SERIES i EDITOR/ASSEMBLER 



i"£J~.-'.'.<< 'z. ».ou-. , "'U». *k ".'•ii'i-r.'.vV.it -.•'"»' ';- : '^'»,f :'js:-»"'»: 







$affffr„ Lfarfj.^.".^* -.. ... i. -»«*...* 



Object Code: 

SUB r 

SUBn 



SUB (HL) 



SUB(IX+d) 



SUB(lY + d) 



1 1 1 1 1 1 1 

1 1 r r r 

i i i I i i i 




110 10 110 




nnnnnnnn 




10 10 1 10 




110 1110 1 




10 10 1 10 




ddd'ddddd 




1111110 1 




10 10 1 10 




l l l I I l I 
dddddddd 

i i i i I I I 



D6 



96 



DD 



96 



FD 



96 



r identifies registers A, B, C, D, E, H or L assembled as follows in the object 
code field above: 



Register 


r 


A = 


111 


B 


000 


C 


001 


D = 


010 


E 


011 


H 


100 


L 


101 


Description: 





The s operand is subtracted from the contents of the Accumulator, and the result 
is stored in the Accumulator. 



112 



I^^VajS^aMKiahffitt^tt.'iJ'. - ' '.S.T/V&i.'JEZ'. 



''^'f ....5V ^z^f'l 



^^^^^— M 



Instruction 

SUBr 

SUBn 
SUB (HL) 
SUB(IX+d) 
SUB(IY+d) 



M 
Cycles 

1 

2 

2 
5 
5 



T States 

4 - 

7(4,3) 

7(4,3) 

19(4,4,3,5,3) 

19(4,4,3,5,3) 



4 MHz 
E.T. in |xs 

1.00 
1.75 
1.75 
4.75 
4.75 



Condition Bits Affected: 



S: Set if result is negative; reset otherwise 

Z: Set if result is zero; reset otherwise 

H: Set if borrow from Bit 4; reset otherwise 

P/V: Set if overflow; reset otherwise 

N: Set 

C: Set if borrow; reset otherwise 

Example: 

If the Accumulator contains 29H and register D contains 1 1H, after the 

execution of 

SUB D 

the Accumulator will contain 18H. 



Operation: A <J A — S — CY 



SuBtract with borrow (Carry) 



Operands: A, s 



Format: 
Mnemonic: SBC 

The s operand is any of r, n, (HL), (IX+d) or (IY+d) as defined for the 
analogous ADD instructions. These various possible opcode-operand 
combinations are assembled as follows in the object code: 



Object Code: 

SBC A, r 



SBC A, n 



1 








1 


1 


r 


r 


r 












1 


1 





1 


1 


1 


1 















n 


n 


1 
n 

l 


n 


n 


n 


n 


n 



DE 



113 



SERIES I EDITOR/ASSEMBLER 



SBC A, (HL) 



SBC A, (IX+d) 



SBC A,(IY + d) 



1 








1 


1 


1 


1 













1 


1 





1 


1 


1 





1 










1 








1 


1 


1 


1 













d 


d 


d 


d 


d 


d 


d 


d 










1 


1 


1 


1 


1 


1 





1 






1 








1 


1 


1 


I 

1 

i 






d 


d 


d 


d 


d 


d 


d 


d 



9E 



DD 



9E 



FD 



9E 



r identifies registers A, B, C, D, E, H, or L assembled as follows in the object 
code field above: 



lister 


r 


A = 


111 


B 


000 


C 


001 


D = 


010 


E 


011 


H = 


100 


L 


101 



Description: 

The s operand, along with the Carry Flag ("C" in the F register) is subtracted 
from the contents of the Accumulator, and the result is stored in the 
Accumulator. 



114 



8 BIT ARIT HMETIC AND LOGICAL GROUP 





M 




4 MHz 


Instruction 


Cycles 


T States 


EX in |xs 


SBC A, r 


1 


4 


1.00 


SBC A, n 


2 


7(4,3) 


1.75 


SBC A, (HL) 


2 


7(4,3) 


1.75 


SBC A, (IX+d) 


5 


19(4,4,3,5,3) 


4.75 


SBC A, (IY+d) 


5 


19(4,4,3,5,3) 


4.75 



Condition Bits Affected: 

S: Set if result is negative; reset otherwise 

Z: Set if result is zero; reset otherwise 

H: Set if borrow from Bit 4; reset otherwise 

P/V: Set if overflow; reset otherwise 

N: Set 

C: Set if borrow; reset otherwise 

Example 1: 

If the Carry Flag is set, the Accumulator contains 16H, the HL register pair 
contains 3433H, and address 3433H contains 05H, after the execution of 

SBC A,(HL) 

the Accumulator will contain 10H. 

Example 2: 

If the Carry Flag is set, the Accumulator contains 21H and register B contains 
then after the execution of 

SBC A,B 

the Accumulator contains 20H. 



Operation: A(lA-Q-S 

Format: 

Mnemonic: AND Operands: s 

The s operand is any of r, n, (HL), (IX+d) or (IY+d), as defined for the 
analogous ADD instructions. These various possible opcode-operand 
combinations are assembled as follows in the object code: 



S3 



115 



KlSaJiaLl„'^ '. '1 ^.JI..!^.!.:IIII_^.i,jll...^l...lL,.I. ;.l 2„I.J^iX»Z^^^^ 






Object Code: 
ANDr 

ANDn 



AND (HL) 



AND(IX+d) 



AND(IY + d) 



1 





1 








r 


r 


r 






1 


1 


1 








1 


1 











n 


n 


n 


n 


n 


n 


n 


n 






1 





1 








1 


1 









1 


1 





1 


1 


1 





1 






1 





1 








1 


1 











d 


d 


d 


d 


d 


d 


d 


d 










1 


1 


1 




1 


1 





1 










1 





1 








1 


1 









d 


d 


d 


d 


d 


d 


d 


d 



E6 



A6 



DD 



A6 



FD 



A6 



r identifies register A, B, C, D, E, H or L assembled as follows in the object 
code field above: 



gister 


r 


A = 


111 


B = 


000 


C 


001 


D = 


010 


E 


011 


H = 


100 


L 


101 



116 



8 BIT ARITHMETIC AND LOGICAL GROUP 



fe^^^*TMag»'*«Psy»gy»»»sg^\y ;.;.■■*•? ■■-^-g-;-- 1 



Description: 

A logical AND operation, Bit by Bit, is performed between the byte specified 
by the s operand and the byte contained in the Accumulator; the result is stored 
in the Accumulator. 





M 




4 MHz 


Instruction 


Cycles 


; T States 


E.T. in (xs 


ANDr 


1 


4 


1.00 


ANDn 


2 


7(4,3) 


1.75 


AND (HL) 


2 


7(4,3) 


1.75 


AND(IX+d) 


5 


19(4,4,3,5,3) 


4.75 


AND(IX + d) 


5 


19(4,4,3,5,3) 


4.75 


Condition Bits Affected: 






S: Set if result 


is negative; reset otherwise 




Z: Set if result 


is zero; 


reset otherwise 




H: Set 








P/V: Set if parity 


even; r 


eset otherwise 




N: Reset 








C: Reset 









Table of AND Values: 



IF 
A B 


Then 
A (After) 




1 

1 

1 1 






1 



Example: 

If the B register contains 7BH (01111011) and the Accumulator contains C3H 
(11000011), after the execution of 

AND B 

the Accumulator will contain 43H (0100001 1). 



0__ 
rl S 

Operation: A <1 A OS 

Format: 

Mnemonic: OR Operands: s 



117 



SERIES I EDIT OR/ASSEf 



The s operand is any of r, n, (HL), (IX+d), or (IY+d), as defined for the 
analogous ADD instructions. These various possible opcode-operand 
combinations are assembled as follows in the object code: 



Object Code: 
ORr 



ORn 



OR (HL) 
OR (IX+d) 



OR(lY+d) 



1 1 1 1 1 1 1 

1 1 1 r r r 

I I I I i I i 




1 1 1 1 1 1 1 

11110 110 

I I I I i i i 




nnnnnnnn 

I I i I i i i 




10 110 110 

1 1 1 1 1 1 1 




1 1 1 1 1 1 1 

110 1110 1 

1 1 1 1 1 1 1 




1 1 1 1 1 1 1 

1 1 I 1 1 

1 1 1 1 1 1 1 




1 1 1 1 1 1 1 

dddddddd 

i i i i i i i 




1 1 1 1 1 1 1 

1111110 1 

i i i i i i i 




1 1 1 1 1 1 1 

10 110 110 

1 1 1 1 1 1 1 




1 1 1 1 1 1 1 
dddddddd 

i 



F6 



B6 



DD 



B6 



FD 



B6 



r identifies register A, B, C, D, E, H or L assembled as follows in the object 
code field above: 

Register r 

A = 111 

B = 000 

C = 001 

D = 010 

E = 011 

H = 100 

L = 101 



118 



8 BIT ARITHMETIC AND LOGICAL GROUP 



Description: 

A logical OR operation, Bit by Bit, is performed between the byte specified by 
the s operand and the byte contained in the Accumulator; the result is stored in 
the Accumulator, 



Instruction 


M 
Cycles 


: T States 


4 MHz 
E.T. in jxs 


ORr 
ORn 
OR (HL) 
OR(IX+d) 
OR(IY+d) 


1 

2 
2 
5 
5 


4 

7(4,3) 

7(4,3) 

19(4,4,3,5,3) 

19(4,4,3,5,3) 


1.00 
1.75 
1.75 
4.75 
4.75 


Condition Bits Affected: 






S: Set if i 
Z: Set if i 
Hi Reset 
P/V: Set if] 
N: Reset 
C: Reset 


result is negative; reset otherwise 
result is zero; reset otherwise 

parity even; reset otherwise 




Table of OR Values: 






IF 
A B 


Then 

A (After) 








1 

1 

1 1 



1 
1 
1 







Example: 

If the H register contains 48H (01001000) and the Accumulator contains 
12H (00010010), after the execution of 

OR H 

the Accumulator will contain 5AH (01011010). 

XOR S exclusive OR 

Operation: A <lA©S 

Format: 

Mnemonic: XOR Operands: s 



119 



SERIES E EDI TOR/ASSEM BLE 



l.'~'. ' ?X?^...1«^y^^^ , ^ H 



The s operand is any of r, n, (HL), (IX+ d) or (IY+ d), as defined for the 
analogous ADD instructions. These various possible opcode-operand 
combinations are assembled as follows in the object code: 



Object Code: 
XORr 



XORn 



XOR (HL) 



XOR(IX+d) 



XOR(IY+d) 



1 1 ! I 1 1 I 
1 1 1 r r r 

! i 1 1 1 1 1 




1 1 1 1 1 1 1 

1110 1110 




nnnnnnnn 




10 10 1110 




110 1110 1 

i i i i I i i 




l l 1 1 1 1 I 
10 10 1110 




dddddddd 

i i i i i i i 




1111110 1 




10 10 1110 




dddddddd 



EE 



AE 



DD 



AE 



FD 



AE 



r identifies registers A, B, C, D, E, H or L assembled as follows in the object 
code field above: 

Register r 

A = 111 

B = 000 

C = 001 

D = 010 

E = 011 

H = 100 

L = 101 



gffiK^^^^^^^^^^^^^^^^^^^^^ ^ ^ ^^ ^ ^^^a 



120 



8 BIT ARITHMETIC AND LOGICAL GROUP 



Description: 

A logical exclusive-OR operation, bit by bit, is performed between the byte 
specified by the s operand and the byte contained in the Accumulator; the result 
is stored in the Accumulator. 



Instruction 

XORr 
XORn 
XOR (HL) 
XOR (IX+ d) 
XOR(IY+d) 



M 
Cycles 

1 

2 
2 
5 
5 



T States 

4 

7(4,3) 

7(4,3) 

19(4,4,3,5,3) 

19(4,4,3,5,3) 



4 MHz 
E.T. in (xs 

1.00 
1.75 
1.75 
4.75 
4.75 



Condition Bits Affected: 

S: Set if result is negative; reset otherwise 

Z: Set if result is zero; reset otherwise 

H: Reset 

P/V: Set if parity even; reset otherwise 

N: Reset 

C: Reset 



?<s> l\ 



w^ 



a a 



\ \ \ o 



* \ 



\ >i o 



6 ' I o ° 



Table of XOR V 


r alues: 


IF 


Then 


A B 


A (After) 








1 


1 


1 


1 


1 1 







Note: in Table above that any two like numbers will result in zero. 

Example 1: 

If the Accumulator contains 96H (100101 10), after the execution of 

XOR 5DH (Note:5DH = 01011101) 

the Accumulator will contain CBH (11001011). 

Example 2: 

The instruction 
[ XOR Aj 
will zero the Accumulator. 



121 



.v..r**'.s^gr.'^<: ', ... .■— * » .v..-,/ Ji F.^ ^fA**-'- -*Mi~jim:-,* ^!iiSi^umrf)si^r47>^aii^mmm0i<!m^xmmi'aifMfZfj^MS 



Com Pare 



Operation: A— S 

Format: 

Mnemonic: CP Operands: s 

The s operand is any of r, n, (HL), (IX+d) or (lY+d), as defined for the 
analogous ADD instructions. These various possible opcode-operand 
combinations are assembled as follows in the object code; 



Object Code: 
CPr 



CPn 



CP (HL) 



CP(IX+d) 



CP(lY+d) 



1 1 1 1 1 1 1 

1 1 1 1 r r r 

i i i i i i i 




1 1 l 1 ! 1 1 
11111110 

1 1 1 ! 1 1 1 




1 1 1 I 1 1 1 

nnnnnnnn 

i i i i i i i 




I l I l 1 1 I 

10 111110 






I 1 I l l I 1 
110 1110 1 




10 111110 

1 1 1 1 1 1 1 




dddddddd 

i i i i i i i 




1111110 1 

i i i i i i i 




i I I l 1 1 1 

10 111110 

1 1 1 1 1 1 1 




1 1 1 I 1 1 1 

dddddddd 

ii 



FE 



BE 



DD 



BE 



FD 



BE 



r identifies register A, B, C, D, E, H or L assembled as follows in the object 
code field above: 



122 



8 BIT ARITHMETIC AND LOGICAL GROUP 



Register 


r 


A = 


111 


B = 


000 


C = 


001 


D = 


010 


E = 


011 


H = 


100 


L 


101 


Description: 





The contents of the s operand are compared with the contents of the 
Accumulator. If there is a true compare, a flag is set. 

M 4 MHz 

Instruction Cycles T States E.T. in (xs 

CPr 14 1.00 

CPn 2 7(4,3) 1.75 

CP(HL) 2 7(4,3) 1.75 

CP(IX+d) 5 19(4,4,3,5,3) 4.75 

CP(IY+d) 5 19(4,4,3,5,3) 4.75 

Condition Bits Affected: 

S: Set if result is negative; reset otherwise 

Z: Set if result is zero; reset otherwise 

H: Set if borrow from Bit 4; reset otherwise 

P/V: Set if overflow; reset otherwise 

N: Set 

C: Set if borrow in Bit 7; reset otherwise 

Example 1: 

If the Accumulator contains 63H, the HL register pair contains 6000H and 
memory location 6000H contains 60H, the instruction 

CP (HL) 

will result in all the flags being reset except N. 

Example: 2 

If the Accumulator contains 65H and register C also contains 65H, then after the 
execution of 

CP C 

the Z flag will be set. 

See Appendix E for more details of condition codes affected. 



123 



SERIES I EDITOR/ASSEMBLER 



INC r INCrement 

Operation: f () X + 1 



Format: 

Mnemonic: INC Operands: r 

Object Code: 









r 


r 


r 


1 


1 


1 






Description: 

Register r is incremented, r identifies any of the registers A, B, C, D, E, Hor 
L, assembled as follows in the object code. 



Register 




r 


A 


= 


111 


B 


= 


000 


C 


= 


001 


D 


= 


010 


E 


= 


011 


H 


= 


100 


L 


= 


101 



M cycles: 1 T states: 4 4 MHz E.T.: 1.00 

Condition Bits Affected: 

S: Set if result is negative; reset otherwise 

Z: Set if result is zero; reset otherwise 

H: Set if carry from Bit 3; reset otherwise 

P/V: Set if r was 7FH before operation; reset otherwise 

N: Reset 

C: Not affected 

Example: 

If the contents of register D are 28H, after the execution of 

INC D 

the contents of register D will be 29H. 



124 



8 BIT ARITHMETIC AND LOGICAL GROUP 



INC (HL) INCrement 

Operation: (HL)<l(HL) + 1 



Format: 

Mnemonic: INC Operands: (HL) 

Object Code: 

— I | | | | 

34 









1 


1 





1 









Description: 

The byte contained in the address specified by the contents of the HL register 
pair is incremented. 

M cycles: 3 T states: 11(4,4,3) 4 MHz E.T.: 2.75 

Condition Bits Affected: 

S: Set if result is negative; reset otherwise 

Z: Set if result is zero; reset otherwise 

H: Set if carry from Bit 3; reset otherwise 

P/V: Set if (HL) was 7FH before operation; reset otherwise 

N: Reset 

C: Not Affected 

Example: 

If the contents of the HL register pair are 3434H, and the contents of address 
3434H are 82H, after the execution of 

INC (HL) 

memory location 3434H will contain 83H. 

INC(IX+d) INCrement 

Operation: (IX+ d) <1 (IX+ d) + 1 

Format: 

Mnemonic: INC Operands: (IX+ d) 



125 



SERIES I EDITOR/ASSEMBLER 



Object Code: 



1 


1 





1 


1 


1 





1 










1 


1 





1 










d 


d 


d 


d 


d 


d 


d 


d 



DD 



34 



Description: 

The contents of the Index Register IX (register pair IX) are added to a two's 
complement displacement integer d to point to an address in memory. The 
contents of this address are then incremented. 

M cycles: 6 T states: 23(4,4,3,5,4,3) 4 MHz E.T.: 5.75 



Condition Bits Affected: 

S: Set if result is negative; reset otherwise 

Z: Set if result is zero; reset otherwise 

H: Set if carry from Bit 3; reset otherwise 

P/V: Set if (IX+ d) was 7FH before operation; reset otherwise 

N: Reset 

C: Not affected 



Example: 

If the contents of the Index Register pair IX are 2020H, and the memory 
location 2030H contains byte 34H, after the execution of 

INC (IX+ 10H) 

the contents of memory location 2030H will be 35H. 



C(IY + d) 



INCrement 



Operation: (IY+ d) <l(IY+ d) + 1 

Format: 

Mnemonic: INC Operands: (IY+d) 



126 



'.tit. i.;.y..S-«.'*".a! ! z% *. ».':'< 



8 BIT ARI 



"HHHETiC AND LOGICAL GROUP 



Object Code: 



1 


1 


1 


1 


1 


1 





1 














1 


1 





1 














d 


d 


d 


d 


d 


d 


d 


d 



FD 



34 



Description: 

The contents of the Index Register IY (register pair IY) are added to a two's 
complement displacement integer d to point to an address in memory. The 
contents of this address are then incremented. 

M cycles: 6 T states: 23(4,4,3,5,4,3) 4 MHz E.T.: 5.75 

Condition Bits Affected: 

S: Set if result is negative; reset otherwise 

Z: Set if result is zero; reset otherwise 

H: Set if carry from Bit 3; reset otherwise 

P/V: Set if (IY+d) was 7FH before operation; reset otherwise 

N: Reset 

C: Not Affected 



Example: 

If the contents of the Index Register pair IY are 2020H, and the memory 
location 2030H contain byte 34H, after the execution of 

INC (IY+ 10H) 

the contents of memory location 2030H will be 35H. 



to m 



DECrement 



Operation: IT1 <1 ITI - 1 



Format: 

Mnemonic: DEC 



Operands: m 



The m operand is any of r, (HL), (IX+ d) or (IY+ d), as defined for the 
analogous INC instructions. These various possible opcode-operand 
combinations are assembled as follows in the object code: 



ES222I3E23 



127 



SERIES 1 EDITOR/ASSEMBLER 



Object Code: 

DECr 

DEC (HL) 
DEC(IX+d) 



DEC(IY+d) 



1 1 1 1 1 1 1 

r r r 1 1 

i i i i i i i 




1 1 1 1 1 l l 

110 10 1 

1 1 1 1 1 1 1 




1 1 1 1 1 1 1 

110 1110 1 

1 1 1 1 1 1 1 




1 1 1 1 1 1 1 

110 10 1 

1 1 1 1 1 1 1 




1 1 1 1 1 1 1 

dddddddd 

i i i i i i i 




1 1 1 1 1 1 ! 

1111110 1 

i I I I I I I 




1 1 1 1 1 1 1 

1 10 10 1 

1 1 1 1 1 1 1 




I 1 1 1 1 1 1 
dddddddd 

1 l l 1 1 l l 



35 



DD 



35 



FD 



35 



r identifies register A, B, C, D, E, H or L assembled as follows in the object 
code field above: 



giste 


r 


r 


A 


= 


111 


B 


= 


000 


C 


= 


001 


D 


= 


010 


E 


= 


011 


H 


= 


100 


L 


= 


101 



Description: 

The byte specified by the m operand is decremented. 



128 



8 BIT ARITHMETIC AND LOGICAL GROUP 



M 




4 MHz 


Instruction Cycles 


T States 


E.T. in |xs 


DEC i 1 


4 


1.00 


DEC (HL) 3 


11(4,4,3) 


2.75 


DEC(IX+d) 6 


23(4,4,3,5,4,3) 


5.75 


DEC(IY+d) 6 


23(4,4,3,5,4,3) 


5.75 


Condition Bits Affected: 






S: Set if result is negative; reset otherwise 




Z: Set if result is zero; 


reset otherwise 




H: Set if borrow from 


Bit 4; reset otherwise 




P/V: Set if m was 80H before operation; reset otherwise 


N: Set 






C: Not affected 







Example: 

If the D register contains byte 2 AH, after the execution of 

DEC D 

register D will contain 29H. 



129 



GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS 



ma^mmm^am^ms^^^m^^s^mmm^smmt^^^^im^^mmi^^amm^mmmmims^i^smM 



Gener 
CPU Contra 



DAA 

Operation: Decimal-Adjust Accumulator 



Format: 
Mnemonic: DAA 

Object Code: 



Operands: 









1 








1 


1 


1 



Description: 

This instruction modifies the results of addition or subtraction so that the results 
of binary arithmetic are correct for decimal numbers. The Binary Coded 
Decimal (BCD) code uses the 8-bit accumulator as follows: the eight bits are 
broken up into two groups of four bits, which represent a two-digit decimal 
number from 00 to 99. If numbers like this are added with the binary adder in 
the Z-80, answers larger than 10 may result in each decimal place. The DAA 
instruction will "adjust" the answer so that each decimal place has a value of 9 
or less, and so that the digits have the correct decimal value, though they were 
added by a binary circuit. The carry and half-cany flags are used in this 
conversion, as is a circuit that detects digits that are 10 or bigger. 



Operation 



ADD 
ADC 

INC 



SUB 
SBC 
DEC 

NEC 

M cycles: 1 





HEX 




HEX 








Value in 




Value in 


Number 




c 


Upper 


H 


Lower 


Added 


C 


Jefore 


Digit 


Before 


Digit 


to 


After 


DAA 


(bits 7-4) 


DAA 


(bits 3-0) 


Byte 


DAA 





0-9 





0-9 


00 








0-8 





A-F 


06 








0-9 


1 


0-3 


06 








A-F 





0-9 


60 


1 





9-F 





A-F 


66 


1 





A-F 


1 


0-3 


66 


1 


1 


0-2 





0-9 


60 


1 


1 


0-2 





A-F 


66 


1 


1 


0-3 


1 


0-3 


66 


1 





0-9 





0-9 


00 








0-8 


1 


6-F 


FA 





1 


7-F 





0-9 


A0 


1 


1 


6-F 


1 


6-F 


9A 


1 


T states 


:4 4MHzE.T: 1.00 







131 



SERIES I EDITOR/ASSEMBLER 



Condition Bits Affected: 

S: Set if most significant bit of Ace. is 1 after operation; reset otherwise 

Z: Set if Ace. is zero after operation; reset otherwise 

H: See instruction 

P/V: Set if Ace. is even parity after operation; reset otherwise 

N: Not affected 

C: See instruction 



Example: 

If an addition operation is performed between 15 (BCD) and 27 (BCD), simple 
decimal arithmetic gives this result: 

15 

+ 27 



42 

But when the binary representations are added in the Accumulator according to 
standard binary arithmetic, 



0101 
+ 0010 0111 

0011 1100 = 3C 

the sum is not decimal. The DAA instruction adjusts this result so that the 
correct BCD representation is obtained: 

0011 1100 

01 1 ©(adding 06 from table) 



0100 0010 = 42 



CPL 



ComPLement 



Operation: A <1 A 

Format: 

Mnemonic: CPL Operands: 



Object Code: 









1 





1 


1 


1 


1 



2F 



132 



GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS 



Description: 

Contents of the Accumulator (register A) are inverted (one's complement). 
M cycles: 1 T states: 4 4 MHz E.T.: 1.00 

Condition Bits Affected: 



S: 


Not affected 


Z: 


Not affected 


H: 


Set 


P/V: 


Not affected 


N: 


Set 


C: 


Not affected 



Example: 

If the contents of the Accumulator are 1011 0100, after the execution of 

CPL 

the Accumulator contents will be 0100 1011. 



NEG 



NEGate 



Operation: A <l0- A 

Format: 

Mnemonic: NEG Operands: 



Object Code: 










1110 

i i i 


1 


1 





1 




1 1 1 
10 





1 









ED. 



44 



Description: 

Contents of the Accumulator are negated (two's complement). This is the same 
as subtracting the contents of the Accumulator from zero. Note that 80H is left 
unchanged. 

M cycles: 2 T states: 8(4,4) 4 MHz E.T.: 2.00 



133 



SERIES I EDITOR/ASSEMBLER 



mssmmmMSBasmi^^im^^^m^^gmmm^m^mmB^^smis^m^ms^^mammmss^smmsaatimwsm 



Condition Bits Affected: 

S: Set if result is negative; reset otherwise 

Z: vSet if result is zero; reset otherwise 

H: Set if borrow from Bit 4; reset otherwise 

P/V: Set if Ace. was 80H before operation; reset otherwise 

N: Set 

C: Set if Ace. was not 00H before operation; reset otherwise 

Example: 

If the contents of the Accumulator are 



10 1 10 



after the execution of 

NEG 

the Accumulator contents will be 



110 10 



Operation: CY<0 CY 



Format: 
Mnemonic: CCF 

Object Code: 



Operands: 



— I I I I I I I 

111111 

i i i i i i i 



Complement Carry Flag 



3F 



Description: 

The C flag in the F register is inverted. 

M cycles: 1 T states: 4 4 MHz E.T. : 1 .( 

Condition Bits Affected: 



S: 


Not affected 


Z: 


Not affected 


H: 


Previous carry will be copied 


P/V: 


Not affected 


N: 


Reset 


C: 


Set if CY was before operation; reset otherwise 



134 



GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS 



Si r— 

Operation: CY<) 1 

Format: 

Mnemonic: SCF Operands: 

Object Code: 



! ! ! ! ! ! ! 

110 111 

I I I I I I I 



37 



Set Carry Flag 



Description: 

The C flag in the F register is set. 

M cycles: 1 T states: 4 4 MHz E.T. : 1 . 

Condition Bits Affected: 



S: 


Not affected 


Z: 


Not affected 


H: 


Reset 


P/V: 


Not affected 


N: 


Reset 


C: 


Set 



NOP 



No OPeration 



Operation: 

Format: 

Mnemonic: NOP Operands: 



Object Code: 



] ! ! ! ! ! ! 

00000000 

I I I I I I I 



135 



SERIES ! EDITOR/ASSEMBLER 



Description: 

CPU performs no operation during this machine cycle. 
M cycles: 1 T states: 4 4 MHz E.T.: 1.00 

Condition Bits Affected: None 



HA 



Operation: 

Format: 
Mnemonic: HALT 

Object Code: 



Operands: 



I I I I I I I 
1110 110 

I I I I I 1 I 



76 



Description: 

The HALT instruction suspends CPU operation until a subsequent interrupt or 
reset is received. While in the halt state, the processor will execute NOP's to 
maintain memory refresh logic. 

M cycles: 1 T states: 4 4 MHz E.T.: 1.00 
Condition Bits Affected: None 



Operation: IFF<|]0 

Format: 

Mnemonic: DI Operands: 

Object Code: 



1 


1 


1 


1 








1 


1 



F3 



Disable Interrupts 



136 



GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS 



Description: 

DI disables the maskable interrupt by resetting the interrupt enable flip-flops 
(IFF1 and IFF2). Note that this instruction disables the maskable interrupt 
during its execution. 

M cycles: 1 T states: 4 4 MHz EX: 1.00 
Condition Bits Affected: None 

Example: 

When the CPU executes the instruction 

DI 

the maskable interrupt is disabled until it is subsequently re-enabled by an EI 

instruction. The CPU will not respond to an Interrupt Request (INT) signal. 

El 
I Enable Interrupts 

Operation: IFF<J 1 

Format: 

Mnemonic: EI Operands: 



Object Code: 



1 


1 


1 


1 


1 





1 


1 



FB 



Description: 

EI enables the maskable interrupt by setting the interrupt enable flip-flops (IFF1 
and IFF2). Note that this instruction disables the maskable interrupt during its 
execution. 

M cycles: 1 T states: 4 4 MHz E.T.: 1.00 
Condition Bits Affected: None 

Example: 

When the CPU executes instruction 

RETI 

the maskable interrupt is enabled. The CPU will now respond to an Interrupt 
Request (INT) signal. 



137 



SERIES I EDITOR/ASSEMBLER 



IM0 

Operation: 

Format: 
Mnemonic: IM 

Object Code: 



Operands: 



1 


1 


1 





1 


1 





1 







1 











1 


1 






Interrupt Mode 



ED 



46 



Description: 

The IM instruction sets interrupt mode 0. In this mode the interrupting device 
can insert any instruction on the data bus and allow the CPU to execute it. The 
first byte of a multi-byte instruction is read during interrupt acknowledge cycle. 
Subsequent bytes are read in by a normal memory read sequence. 

M cycles: 2 T states: 8(4,4) 4 MHz E.T. : 2.00 
Condition Bits Affected: None 



IM1 



Interrupt Mode 1 



Operation: 

Format: 
Mnemonic: IM 

Object Code: 



Operands: 1 



1 


1 


1 





1 


1 





1 







1 





1 





1 


1 






ED 



56 



138 



GENERAL PURPOSE ARITHMETIC AND CPU CONTROL G ROUPS 



Description: 

The IM instruction sets interrupt mode 1. In this mode the processor will 
respond to an interrupt by executing a restart to location 0038H. 



M cycles: 2 T states: 8(4,4) 
Condition Bits Affected: None 



4 MHz EX: 2. 



IM2 

Operation: 

Format: 
Mnemonic: IM 

Object Code: 



Operands: 2 



1 


1 


1 





1 


1 





1 







1 





1 


1 


1 


1 






Interrupt Mode 2 



ED 



5E 



Description: 

The IM 2 instruction sets interrupt mode 2. This mode allows an indirect call to 
any location in memory. With this mode the CPU forms a 16-bit memory 
address. The upper eight bits are the contents of the Interrupt Vector Register I 
and the lower eight bits are supplied by the interrupting device. 

M cycles: 2 T states: 8(4,4) 4 MHz E.T.: 2.00 
Condition Bits Affected: None 



139 



16 BIT ARITHMETIC GROUP 



16 Bit Arithmetic Group 

ADD HL,ss 

Operation: HL<lHL f SS 

Format: 

Mnemonic: ADD Operands: HL, ss 

Object Code: 



— I 1 | |— - 1 | | 

s s 1 1 

__J I I J I I _l 



Description: 

The contents of register pair ss (any of register pairs BC, DE, HL or SP) are 
added to the contents of register pair HL, and the result is stored in HL. 
Operand ss is specified as follows in the assembled object code. 



egister 




Pair 


ss 


BC 


00 


DE 


01 


HL 


10 


SP 


11 



M cycles: 3 T states: 11(4,4,3) 4 MHz EX: 2.75 
Condition Bits Affected: 



S: 


Not affected 


Z: 


Not affected 


H: 


Set if carry out of Bit 11; reset otherwise 


P/V: 


Not affected 


N: 


Reset 


C: 


Set if carry from Bit 15; reset otherwise 



Example: 

If register pair HL contains the integer 4242H and register pair DE contains 
1111H, after the execution of 

ADD HL, DE 

the HL register pair will contain 5353H. 



141 



SERIES I EDITOR/ASSEMBLER 



Operation: HL<] HL+ SS + CY 

Format: 

Mnemonic: ADC Operands: HL, ss 



ADd with Carry 



Object Code: 






I 1 I I i 

1110 11 

i i i i i 





1 




1 1 1 ! 1 

1 s s 1 

1 1 1 1 1 


1 






ED 



Description: 

The contents of register pair ss (any of register pairs BC, DE, HL or SP) are 
added with the Carry Flag (C flag in the F register) to the contents of register 
pair HL, and the result is stored in HL. Operand ss is specified as follows in the 
assembled object code. 

Register 
Pair ss 



BC 
DE 
HL 
SP 



01 
10 
11 



M cycles: 4 T states: 15(4,4,4,3) 4 MHz E.T.: 3.75 



Condition Bits Affected: 

S: Set if result is negative; reset otherwise 

Z: Set if result is zero; reset otherwise 

H: Set if carry out of Bit 11; reset otherwise 

P/V: Set if overflow; reset otherwise 

N: Reset 

C: Set if carry from Bit 15; reset otherwise 



Example: 

If the register pair BC contains 2222H, register pair HL contains 5437H and the 
Carry Flag is set, after the execution of 

ADC HL, BC 

the contents of HL will be 765 AH. 



142 



16 BIT ARITHMETIC GROUP 



ODv/ riL,SS 

Operation: Hl_OHI_-SS-CY 

Format: 

Mnemonic: SBC Operands: HL, ss 



SuBtract with Carry 



Object Code: 










I I I 

1110 

i i i 


1 


1 





1 




1 1 1 
1 s s 








1 






ED 



Description: 

The contents of the register pair ss (any of register pairs BC, DE, HL or SP) 
and the Cany Flag (C flag in the F register) are subtracted from the contents of 
register pair HL and the result is stored in HL. Operand ss is specified as 
follows in the assembled object code. 

Register 
Pair ss 



BC 
DE 
HL 
SP 



01 
10 
11 



M cycles: 4 T states: 15(4,4,4,3) 4 MHz E.T.: 3.75 



Condition Bits Affected: 

S: Set if result is negative; reset otherwise 

Z: Set if result is zero; reset otherwise 

H: Set if borrow from Bit 12; reset otherwise 

P/V: Set if overflow; reset otherwise 

N: Set 

C: Set if borrow; reset otherwise 



Example: 

If the contents of the HL register pair are 9999H, the contents of register pair 
S DE are 1111H, and the Carry Flag is set, after the execution of 

SBC HL, DE 

the contents of HL will be 8887H. 



143 



SERIES I EDITOR/ASSEMBLER 



ADD IX,pp 

Operation: IX<]IX+pp 

Format: 

Mnemonic: ADD Operands: IX, pp 

Object Code: 



1 


1 





1 


1 


1 





1 










p 


p 


1 








1 



DD 



Description: 

The contents of register pair pp (any of register pairs BC, DE, IX or SP) are 
added to the contents of the Index Register IX, and the results are stored in IX. 
Operand pp is specified as follows in the assembled object code. 



Register 






Pair 


PP 




BC 


00 




DE 


01 




IX 


10 




SP 


11 




M cycles: 


4 T states: 15(4,4,4,3) 4 MHz E 


Condition Bits Affected: 




S: 
Z: 


Not affected 
Not affected 




H: 


Set if carry out of Bit 1 1 


; reset otherwise 


P/V: 


Not affected 




N: 


Reset 




C: 


Set if carry from Bit 15; 


reset otherwise 



Example: 

If the contents of Index Register IX are 3333H and the contents of register pair 
BC are 5555H, after the execution of 

ADD IX, BC 

the contents of IX will be 8888H. 



144 



18 BIT ARITHMETIC GROUP 



ADD !Yrr 

Operation: lY^IY+IT 

Format: 

Mnemonic: ADD Operands: IY, rr 



Object Code: 




I I I 

1111 

i i i 


l l I 
110 1 




I i i 

r r 

i i i 


1 1 1 

10 1 

1 1 1 



FD 



Description: 

The contents of register pair rr (any of register pairs BC, DE, IY or SP) are 
added to the contents of Index Register IY, and the result is stored in IY. 
Operand rr is specified as follows in the assembled object code. 



Register 






Pair 


rr 




BC 


00 




DE 


01 




IY 


10 




SP 


11 




M cycles: 


4 T states: 15(4,4,4,3) 4 MHz E 


Condition Bits Affected: 




S: 


Not affected 




Z: 


Not affected 




H: 


Set if carry out of Bit 11 


reset otherwise 


P/V: 


Not affected 




N: 


Reset 




C: 


Set if carry from Bit 15; 


reset otherwise 



Example: 

If the contents of Index Register IY are 333H and the contents of register pair 
BC are 555H, after the execution of 

ADD IY, BC 

the contents of IY will be 888H. 



145 



SERIES I EDITOR/ASSEMBLER 






INCss 

Operation: SS <0 SS + 1 

Format: 

Mnemonic: INC Operands: ss 

Object Code: 



— I 1 1 1 1 1 1 — 

s s 1 1 

i i [ [ [ i i 



INCrement 



Description: 

The contents of register pair ss (any of register pairs BC, DE, HL or SP) are 
incremented. Operand ss is specified as follows in the assembled object code. 



Register 




Pair 


ss 


BC 


00 


DE 


01 


HL 


10 


SP 


11 



M cycles: 1 T states: 6 4 MHz EX: 1.50 
Condition Bits Affected: None 

Example: 

If the register pair contains 1000H, after the execution of 

INC HL 

HL will contain 1001H. 



INC IX 



INCrement 



Operation: IX<) IX+ 1 

Format: 

Mnemonic: INC Operands: IX 



146 



16 BIT ARITHMETIC GROUP 



Object Code: 










I I I 

l l 1 

i i i 


1 


1 





1 




10 








1 


1 



DD 



23 



Description: 

The contents of the Index Register IX are incremented. 
M cycles: 2 T states: 10(4,6) 4 MHz E.T.: 2.50 

Condition Bits Affected: None 

Example: 

If the Index Register IX contains the integer 3300H after the execution of 

INC IX 

the contents of Index Register IX will be 3301H. 



INCIY 



INCrement 



Operation: IY<llY+1 

Format: 

Mnemonic: INC Operands: IY 

Object Code: 



1 


1 


1 


1 


1 


1 





1 










1 











1 


1 



FD 



23 



Description: 

The contents of the Index Register IY are incremented. 
M cycles: 2 T states: 10(4,6) 4 MHz E.T.: 2.50 

Condition Bits Affected: None 



147 



SERIES I EDITOR/ASSEMBLER 



Example: 

If the contents of the Index Register are 2977H, after the execution of 

INC IY 

the contents of Index Register IY will be 2978H. 

tO SS DECrement 

Operation: SS<1SS-1 

Format: 

Mnemonic: DEC Operands: ss 

Object Code: 









s 


s 


1 





1 


1 



Description: 

The contents of register pair ss (any of the register pairs BC, DE, HL or SP) are 
decremented. Operand ss is specified as follows in the assembled object code. 



Register 




Pair 


ss 


BC 


00 


DE 


01 


HL 


10 


SP 


11 



M cycles: 1 T states: 6 4 MHz EX: 1.50 
Condition Bits Affected: None 

Example: 

If register pair HL contains 100 1H, after the execution of 

DEC HL 

the contents of HL will be 1000H. 



148 



16 BIT ARITHMETIC GROUP 



tU IA 



Operation: IX<0 IX — 1 

Format: 

Mnemonic: DEC Operands: IX 

Object Code: 



1 


1 





1 


1 


1 





1 










1 





1 





1 


1 



DD 



2B 



DECrement 



Description: 

The contents of Index Register IX are decremented. 
M cycles: 2 T states: 10(4,6) 4 MHz EX: 2.50 

Condition Bits Affected: None 

Example: 

If the contents of Index Register IX are 2006H, after the execution of 

DEC IX 

the contents of Index Register IX will be 2005H. 



Dpp IY 

Operation: IY<llY-1 

Format: 

Mnemonic: DEC Operands: IY 



Object Code: 










I I I 

1111 

i i i 


1 


1 





1 




1 1 1 
10 

1 1 1 


1 





1 


1 



FD 



2B 



DECrement 



149 



SERIES I EDITOR/ASSEMBLER 



Description: 

The contents of the Index Register IY are decremented. 

M cycles: 2 T states: 10(4,6) 4 MHz E.T.: 2.50 

Condition Bits Affected: None 

Example: 

If the contents of the Index Register IY are 7649H, after the execution of 

DEC IY 

the contents of Index Register IY will be 7648H. 



150 



ROTATE AND SHIFT GROUP 






BBS S 



..— ■■ ..- ._ ^ - r ^ ~[ 



itate and Shit Group 



Rotate Left Circular Accumulator 



Operation: | CY | $ 7^0 | <J 

A 

Format: 

Mnemonic: RLCA Operands: 

Object Code: 


















1 


1 


1 



07 



Description: 

The contents of the Accumulator (register A) are rotated left: the content of bit 
is moved to bit 1; the previous content of bit 1 is moved to bit 2; this pattern is 
continued throughout the register. The content of bit 7 is copied into the Carry 
Flag (C flag in register F) and also into bit 0. (Bit is the least significant bit.) 

M cycles: 1 T states: 4 4 MHz E.T.: 1.00 
Condition Bits Affected: 



S: 


Not affected 


Z: 


Not affected 


H: 


Reset 


P/V: 


Not affected 


N: 


Reset 


C: 


Data from Bit 7 of Ace 



Example: 

If the contents of the Accumulator are 



7 



4 



1 



10 10 



after the execution of 

RLCA 

the contents of the Carry Flag and the Accumulator will be 

C 7 6 5 4 3 2 10 



1 10 1 



151 



SERIES I EDITOR/ASSEMBLER 



I l WtamJl \ 



tf-i/in* *• 



Operation: 1 - CY <^~ 7 y-0 



2 



Format: 
Mnemonic: RLA 

Object Code: 



A 

Operands: 












1 




1 


1 


1 


1 



Rotate Left Accumulator 



17 



Description: 

The contents of the Accumulator (register A) are rotated left: the content of bit 
is copied into bit 1; the previous content of bit 1 is copied into bit 2; this pattern 
is continued throughout the register. The content of bit 7 is copied into the Carry 
Flag (C flag in register F) and the previous content of the Carry Flag is copied 
into bit 0. Bit is the least significant bit. 

M cycles: 1 T states: 4 4 MHz E.T.: 1.00 

Condition Bits Affected: 

S: Not affected 

Z: Not affected 

H: Reset 

P/V: Not affected 

N: Reset 

C: Data from Bit 7 of Ace. 



Example: 

If the contents of the Carry Flag and the Accumulator are 
C 7 6 5 4 3 2 10 



n ro 1110110 



after the execution of 

RLA 

the contents of the Carry Flag and the Accumulator will be 

C 7 6 5 4 3 2 10 



1110 110 1 



152 



Operation: 1 -^ 7~t) 



A 



Format: 
Mnemonic: RRCA 

Object Code: 



Rotate Right Circular Accumulator 



5jo 



CY 



Operands: 












1 

1 

1 


1 
1 1 

1 


1 



0F 



Description: 

The contents of the Accumulator (register A) are rotated right: the content of bit 
7 is copied into bit 6; the previous content of bit 6 is copied into bit 5; this 
pattern is continued throughout the register. The content of bit is copied into 
bit 7 and also into the Carry Flag (C flag in register F.) Bit is the least 
significant bit. 

M cycles: 1 T states: 4 4 MHz E.T.: 1.00 

Condition Bits Affected: 

S: Not affected 

Z: Not affected 

H: Reset 

P/V: Not affected 

N: Reset 

C: Data from Bit of Ace. 



Example: 

If the contents of the Accumulator are 
7 6 5 4 3 2 10 



10 1 



After the execution of 

RRCA 

the contents of the Accumulator and the Cany Flag will be 

76543210 C 



10 10 1 



153 



SERIES 1 EDITOR/ASSEMBLER 



Operation:4> | 7-Q | -Q | CY \} 

A 

Format: 

Mnemonic: RRA Operands: 

Object Code: 



i i r i 
1 

I I I L 



1 1 1 



Rotate Right Accumulator 



IF 



Description: 

The contents of the Accumulator (register A) are rotated right: the content of 
bit 7 is copied into bit 6; the previous content of bit 6 is copied into bit 5; this 
pattern is continued throughout the register. The content of bit is copied into 
the Carry Flag (C flag in register F) and the previous content of the Carry Flag 
is copied into bit 7. Bit is the least significant bit. 



M cycles: 



T states: 4 



4MHzE.T: l.C 



Condition Bits Affected: 



S 

z 

H 

P/V: 

N: 

C: 



Not affected 

Not affected 

Reset 

Not affected 

Reset 

Data from Bit * 



of Ace. 



Example: 

If the contents of the Accumulator and the Carry Flag are 
7 6 5 4 3 2 10 C 



1110 1 



after the execution of 

RRA 

the contents of the Accumulator and the Carry Flag will be 

7 6 5 4 3 2 10 C 



1110 1 



154 



Rotate Left Circular 



Operation: CY $• 7<CrO 



< J\~7$o\ <? 



Format: 

Mnemonic: RLC Operands: r 



Object Code: 








110 

i i i 


1 





1 
1 1 

1 




1 1 l 


1 1 1 





r 


l 
r r 

I 



CB 



Description: 

The eight-bit contents of register r are rotated left: the content of bit is copied 
into bit 1; the previous content of bit 1 is copied into bit 2; this pattern is 
continued throughout the register. The content of bit 7 is copied into the Carry 
Flag (C flag in register F) and also into bit 0. Operand r is specified as follows 
in the assembled object code: 



Register 


r 


B 


000 


C 


001 


D 


010 


E 


011 


H 


100 


L 


101 


A 


111 



Note: Bit is the least significant bit. 

M cycles: 2 T states: 8(4,4) 4MHzE.T.:2. 

Condition Bits Affected: 

S: Set if result is negative; reset otherwise 

Z: Set if result is zero; reset otherwise 

H: Reset 

P/V: Set if parity even; reset otherwise 

N: Reset 

C: Data from Bit 7 of source register 



155 



SERIES i EDITOR/ASSEMBLER 



•■:■■■- - •;.:::.-,.■:■■ -;- ; - 1 



Example: 

If the contents of register r are 
7 6 5 4 3 2 10 



10 10 



after the execution of 

RLC r 

the contents of the Carry Flag and register r will be 

C 7 6 5 4 3 2 10 



1 10 



Operation: QY (p- 7<)0 



Format: 
Mnemonic: RLC 



(HL) 

Operands: (HL) 



Rotate Left Circular 



Object Code: 



1 


1 








1 





1 


1 



















1 


1 






CB 



06 



Description: 

The contents of the memory address specified by the contents of register pair 
HL are rotated left: the content of bit is copied into bit 1; the previous content 
of bit 1 is copied into bit 2; this pattern is continued throughout the byte. The 
content of bit 7 is copied into the Carry Flag (C flag in register F) and also into 
bit 0. Bit is the least significant bit. 

M cycles: 4 T states: 15(4,4,4,3) 4 MHz E.T.: 3.75 



156 



ROTATE AND SHIFT GROUP 



s r ..z^^w:jT.,-%.-i.:^'.. M -<A^.&! .'...; 



Condition Bits Affected: 

S: Set if result is negative; reset otherwise 

Z: Set if result is zero; reset otherwise 

H: Reset 

P/V: Set if parity even; reset otherwise 

N: Reset 

C: Data from Bit 7 of source register 

Example: 

If the contents of the HL register pair are 2828H, and the contents of memory 
location 2828H are 



7 



4 



1 



1 I I I I 1 I 



after the execution of 

RLC (HL) 

the contents of the Carry Flag and memory locations 2828H will be 

C 76543210 



1 10 1 



iLL/ 1 1/\ i Gl 



Operation: 



<j| 7Q-0 IQ-J 



CY 1 70-O 



(IX+d) 



Format: 

Mnemonic: RLC Operands: (IX+d) 

Object Code: 



1 


1 





1 


1 


1 





1 








1 


1 








1 





1 


1 








d 


d 


d 


d 


d 


d 


d 


d 























1 


1 






DD 



CB 



06 



Rotate Left Circular 



157 



Description: 

The contents of the memory address specified by the sum of the contents of the 
Index Register IX and a two's complement displacement integer d, are rotated 
left: the contents of bit is copied into bit 1; the previous content of bit 1 is 
copied into bit 2; this pattern is continued throughout the byte. The content of 
bit 7 is copied into the Carry Flag (C flag in register F) and also into bit 0. Bit 
is the least significant bit. 

M cycles: 6 T states: 23(4,4,3,5,4,3) 4 MHz E.T.: 5.7.5 



Condition Bits Affected: 

S: Set if result is negative; reset otherwise 

Z: Set if result is zero; reset otherwise 

H: Reset 

P/V: Set if parity even; reset otherwise 

N: Reset 

C: Data from Bit 7 of source register 



Example: 

If the contents of the Index Register IX are 1000H, and the contents of memory 
location 1002H are 

7 6 5 4 3 2 10 



10 10 



after the execution of 

RLC (IX+ 2H) 

the contents of the Carry Flag and memory location 1002H will be 

C 7 6 5 4 3 2 10 



10 1 



!LC(IY+d) 



Operation: CY Q l 7Q-Q 



I 



(IY+d) 



Rotate Left Circular 



Format: 

Mnemonic: RLC Operands: (IY+d) 



158 



Sga&H> "sa*£Slt^JiA'sV.:~llJ \ 



ROTATE AND SHIFT GROUP 



I 



Object Code: 



1 


1 


1 




1 


1 


I 
1 

i 






1 


1 








1 





1 


1 






d 


d 


d 


d 


d 


d 


d 


d 





















1 


1 






FD 



CB 



06 



Description: 

The contents of the memory address specified by the sum of the contents of the 
Index Register IY and a two's complement displacement integer d are rotated 
left: the content of bit is copied into bit 1; the previous content of bit 1 is 
copied into bit 2; this process is continued throughout the byte. The content of 
bit 7 is copied into the Carry Flag (C flag in register F) and also into bit 0. Bit 
is the least significant bit. 

M cycles: 6 T states: 23(4,4,3,5,4,3) 4 MHz E.T.: 5.75 
Condition Bits Affected: 



S: Set if result is negative; reset otherwise 

Z: Set if result is zero; reset otherwise 

H: Reset 

P/V: Set if parity even; reset otherwise 

N: Reset 

C: Data from Bit 7 of source register 



Example: 

If the contents of the Index Register IY are 1000H, and the contents of memory 
location 1002H are 



7 



1 



1 0|0|0|1|0|0|0 



159 



SERIES i EDITOR/ASSEMBLER 



| 



after the execution of 

RLC (IY+2H) 

the contents of the Carry Flag and memory location 1002H will be 

C 7 6 5 4 3 2 10 



1 10 1 



Rotate Left 



Operation:'- CY <)- 7<)-Q ^F 



m 



Format: 



Mnemonic: RL Operands: m 

The m operand is any of r, (HL), (IX+d) or (IY+d), as defined for the 
analogous RLC instructions. These various possible opcode-operand 
combinations are specified as follows in the assembled object code: 



Object Code: 
RLr 



RL (HL) 



RL(IX+d) 



110 10 11 

1 1 1 1 1 1 1 




1 1 1 1 1 1 1 

1 r r r 

i i i i i i i 




1 1 l l l i I 
110 10 11 

1 1 1 1 1 1 1 




1 1 1 1 1 1 1 
10 1 10 




1 1 1 1 1 1 1 

110 1110 1 

1 1 1 1 1 1 1 




1 1 1 1 1 1 1 
110 10 11 

1 1 I 1 1 1 1 




dddddddd 

i i i i i i i 




1 1 l I I l l 
10 1 10 

1 1 



CB 



CB 



16 



DD 



CB 



16 



160 



ROTATE AND SHIFT GROUP 



^^^^^^^^^^^^^^^^^^^^^^ ^^^^^ 



'i?^2CM3mj^ ''^'Xwt^^aWfcB 



RL(IY + d) 



1 


1 


1 


1 


1 


1 





1 








1 


1 








1 





1 


1 












d 


d 


d 


d 


d 


d 


d 


d 



















1 





1 


1 






FD 



CB 



16 



r identifies register B, C, D, E, H, L or A specified as follows in the assembled 
object code above: 



Register 


r 


B 


000 


C 


001 


D 


010 


E 


011 


H 


100 


L 


101 


A 


111 



Description: 

The contents of the rn operand are rotated left: the content of bit is copied into 
bit 1; the previous content of bit 1 is copied into bit 2; this pattern is continued 
throughout the byte. The content of bit 7 is copied into the Carry Flag (C flag in 
register F) and the previous content of the Carry Flag is copied into bit 0. Bit 
is the least significant bit. 



Instruction 

RLr 
RL (HL) 
RL(IX+d) 
RL(IY+d) 



M 
Cycles 

2 
4 
6 
6 



T States 

8(4,4) 

15(4,4,4,3) 

23(4,4,3,5,4,3) 

23(4,4,3,5,4,3) 



4 MHz 
E.T. in (xs 

2.00 
3.75 

5.75 
5.75 



Condition Bits Affected: 

S: Set if result is negative; reset otherwise 

Z: Set if result is zero; reset otherwise 

H: Reset 

P/V: Set if parity even; reset otherwise 

N: Reset 

C: Data from Bit 7 of source register 



raaiflBfeawsiwigH 



161 



SERIES I EDITOR/ASSEMBLER 



Example: 

If the contents of the Carry Flag and register D are 
C 7 6 5 4 3 2 10 



10 1111 



after the execution of 

RL D 

the contents of the Carry Flag and register D will be 

C 76 5 43210 



1 11110 



RRCm 



Rotate Right Circular 



^cTT^oolo 



Operation: lr) | 7ftQ [ 1ft | QY 

m 

Format: 

Mnemonic: RRC Operands: m 

The m operand is any of r, (HL), (IX +d) or (IY+d), as defined for the 
analogous RLC instructions. These various possible opcode-operand 
combinations are specified as follows in the assembled object code: 



Object Code: 



RRCr 



RRC (HL) 



1 


1 








1 





1 


1 






















1 


r 


r 


r 










1 


1 








1 





1 


1 






















1 


1 


1 






CB 



CB 



0E 



162 



ROTATE AND SHIFT GROUP 



RRC(IX+d) 



RRC(IY+d) 



1 1 1 1 1 1 1 

110 1110 1 

1 1 1 1 1 1 1 




1 1 1 1 1 1 1 
110 10 11 

1 1 1 1 1 1 1 




dddddddd 




l l l l I I I 
1110 

I 1 1 1 1 1 1 




1 1 1 1 1 1 I 

1111110 1 

1 1 1 1 1 1 I 




1 1 1 1 1 1 1 

110 10 11 

1 1 1 1 1 1 1 




1 1 1 1 1 I 1 
dddddddd 

i i i i i i I 




I I i i i i i 
1110 

I 1 1 1 1 1 1 



DD 



CB 



0E 



FD 



CB 



0E 



r identifies register B, C, D, E, H, L or A specified as follows in the assembled 
object code above: 

Register r 

B 000 

C 001 

D 010 

E 011 

H 100 

L 101 

A 111 



Description: 

The contents of operand m are rotated right: the content of bit 7 is copied into 
bit 6; the previous content of bit 6 is copied into bit 5; this pattern is continued 
throughout the byte. The content of bit is copied into the Carry Flag (C flag in 
the F register) and also into bit 7. Bit is the least significant bit. 



163 



SERIES S EDITOR/ASSEMBLER 



M 




4 MHz 


Instruction Cycles 


T States 


E.T. in |is 


RRCr 2 


8(4,4) 


2.00 


RRC (HL) 4 


15(4,4,4,3) 


3.75 


RRC(IXH-d) 6 


23(4,4,3,5,4,3) 


5.75 


RRC(IY+d) 6 


23(4,4,3,5,4,3) 


5.75 


Condition Bits Affected: 






S: Set if result is negative; reset otherwise 




Z: Set if result is zero; 


reset otherwise 




H: Reset 






P/V: Set if parity even; r 


eset otherwise 




N: Reset 






C: Data from Bit of 


source register 




Example: 






If the contents of register A are 




7 6 5 4 3 2 1 








110 1 



after the execution of 

RRC A 

the contents of register A and the Carry Flag will be 

7 6 5 4 3 2 10 C 



110 1 



RKHK& 
h m 



Operation:^) | 7-r)Q J-0 [CY 
Format: 



n 



m 



Rotate Right 



Mnemonic: RR Operands: m 

The m operand is any of r, (HL), (IX+ d) or (IY+ d), as defined for the 
analogous RLC instructions. These various possible opcode-operand 
combinations are specified as follows in the assembled object code: 



164 



ROTATE AND SHIFT GROUP 



Object Code: 

RRr 



RR (HL) 



RR(IX+d) 



RR(IY+d) 



1 1 1 1 1 1 1 
110 10 11 

II 




1 1 1 1 1 1 1 

1 1 r r r 

i i i i i i i 




110 10 11 

1 1 1 1 1 1 1 




1 1 1 1 1 1 1 
11110 




110 1110 1 

1 1 1 1 1 1 1 




1 1 1 1 1 1 1 
110 10 11 

1 1 1 1 1 1 1 




1 1 ! 1 1 1 1 

dddddddd 

i i i i i i i 




11110 




1111110 1 

1 1 1 1 1 1 1 




1 1 1 1 1 1 1 
110 10 11 

1 1 1 1 1 1 1 




1 1 1 1 1 1 1 
dddddddd 

i i i i i i i 




II 

11110 

1 1 1 1 1 1 1 



CB 



CB 



IE 



DD 



CB 



IE 



FD 



CB 



IE 



r identifies registers B, C, D, E, H, L or A specified as follows in the assembled 
object code above: 

Register r 

B 000 

C 001 

D 010 

E 011 

H 100 

L 101 

A 111 



165 



SERIES i EDITOR/ASSEMBLER 



"■■z<>>;,>:<T~~,~::: ■.W..".-.:^--fe;. '■;/■'■-■ -'> -■?.;■,■■'-';' ■, 



Description: 

The contents of operand m are rotated right: the contents of bit 7 is copied into 
bit 6; the previous content of bit 6 is copied into bit 5; this pattern is continued 
throughout the byte. The content of bit is copied into the Cany Flag (C flag in 
register F) and the previous content of the Carry Flag is copied into bit 7. Bit 
is the least significant bit. 



Instruction 

RRr 
RR (HL) 
RR(IX+d) 
RR (IY+ d) 



M 
Cycles 

2 
4 
6 
6 



T States 

8(4,4) 
15(4,4,4,3) 
23(4,4,3,5,4,3) 
23(4,4,3,5,4,3) 



4 MHz 
E.T. in |xs 

2.00 
3.75 
5.75 
5.75 



Condition Bits Affected: 

S: Set if result is negative; reset otherwise 

Z: Set if result is zero; reset otherwise 

H: Reset 

P/V: Set if parity is even; reset otherwise 

N: Reset 

C: Data from Bit of source register 

Example: 

If the contents of the HL register pair are 4343H, and the contents of memory 
location 4343H and the Carry Flag are 



7 


6 


5 


4 


3 


2 


1 





c 


1 


1 





1 


1 


1 





1 






after the execution of 

RR (HL) 

the contents of location 4343H and the Carry Flag will be 

7 6 5 4 3 2 10 C 



110 1110 1 



SLA m 



Operation: [CYJ < H 7<>0 | <h0 

m 

Format: 

Mnemonic: SLA Operands: m 



Shift Left Arithmetic 



166 



ROTATE AND SHIFT GROUP 



The m operand is any of r, (HL), (IX+d) or (IY + d), as defined for the 
analogous RLC instructions. These various possible opcode-operand 
combinations are specified as follows in the assembled object code: 



Object Code: 

SLAr 



SLA (HL) 



SLA (IX+d) 



SLA (IY+d) 



110 10 11 




1 r r r 

i i i i i i i 




I l l l 1 1 1 

110 10 11 

1 I 1 1 1 1 1 




10 1 10 

1 1 1 1 1 1 1 




! 1 1 1 1 1 1 

110 1110 1 

1 1 1 1 1 1 1 




110 10 11 

1 1 1 1 I I 1 




1 1 1 1 1 1 1 

dddddddd 

i i i i i i i 




10 1 10 




1111110 1 

1 1 1 1 1 1 1 




1 1 1 1 1 1 1 

110 10 11 

1 1 1 1 1 1 1 




I 1 1 1 1 1 1 

dddddddd 

i i i i i i i 




i I i I I I 1 
10 1 10 

1 1 1 1 1 1 1 



CB 



CB 



26 



DD 



CB 



26 



FD 



CB 



r identifies registers B, C, D, 
object code field above: 



26 



E, H, L or A specified as follows in the assembled 



167 



SERIES EDITOR/ASSEMBLE 



■■ 



'.' :UU»Mi&Si 



Register 


r 


B 


000 


C 


001 


D 


010 


E 


011 


H 


100 


L 


101 


A 


111 


Description 


: 



An arithmetic shift left is performed on the contents of operand m: bit is reset, 
the previous content of bit is copied into bit 1 , the previous content of bit 1 is 
copied into bit 2; this pattern is continued throughout; the content of bit 7 is 
copied into the Carry Flag (C flag in register F). Bit is the least significant bit. 



M 




4 MHz 


Instruction Cycles 


T States 


E.T. in |xs 


SLA r 2 


8(4,4) 


2.00 


SLA (HL) 4 


15(4,4,4,3) 


3.75 


SLA(IX+d) 6 


23(4,4,3,5,4,3) 


5.75 


SLA(IY+d) 6 


23(4,4,3,5,4,3) 


5.75 


Condition Bits Affected: 






S: Set if result is negative; reset otherwise 




Z: Set if result is zero; 


reset otherwise 




H: Reset 






P/V: Set if parity is even; 


reset otherwise 




N: Reset 






C: Data from Bit 7 







Example: 

If the contents of register L are 
7 6 5 4 3 2 10 



10 1 10 1 



after the execution of 

SLA L 

the contents of the Carry Flag and register L will be 

C 7 6 5 4 3 2 10 



1 110 10 



168 



ROTATE AND SHIFT GROUP 



<S$^Bj:F^~('"& 



Shift Right Arithmetic 



Operation: 
Format: 



7-QO -Q CY 



J? 



m 



Mnemonic: SRA Operands: m 

The m operand is any of r, (HL), (IX+ d) or (IY+ d), as defined for the 
analogous RLC instructions. These various possible opcode-operand 
combinations are specified as follows in the assembled object code: 



Object Code: 
SRAr 



SRA (HL) 



SRA(IX+d) 



1 1 1 1 1 1 1 

110 10 11 

1 1 1 1 1 1 1 




1 1 1 1 I 1 1 

1 1 r r r 

i i i I I I I 




1 1 1 1 1 l I 

110 10 11 

1 1 1 1 1 1 1 




1 1 1 1 1 1 1 
10 1110 

1 1 1 1 1 1 1 




110 1110 1 

1 1 1 1 1 1 1 




1 1 1 1 1 ! 1 

110 10 11 

1 I 1 1 1 1 1 




dddddddd 

i 




1 I I i i i i 
10 1110 

II 



CB 



CB 



2E 



DD 



CB 



2E 



169 



SERIES I EDITOR/ASSEMBLER 



SRA(IY+d) 



1 


1 


1 


1 


1 


1 





1 






1 


1 








1 





1 


1 






d 


d 


d 


d 


d 


d 


d 


d 












I 





1 


1 


1 






FD 



CB 



2E 



r means register B,C,D,E,H,LorA specified as follows in the assembled 
object code field above: 

Register r 

B 000 

C 001 

D 010 

E 011 

H 100 

L 101 

A 111 



An arithmetic shift right is performed on the contents of operand m: the content 
of bit 7 is copied into bit 6; the previous content of bit 6 is copied into bit 5; this 
pattern is continued throughout the byte. The content of bit is copied into the 
Carry Flag (C flag in register F), and the previous content of bit 7 is unchanged. 
Bit is the least significant bit. 



Instruction 


M 
Cycles 


T States 


4 MHz 
E.T. in |xs 


SRAr 
SRA (HL) 
SRA(IX+d) 
SRA(IY+d) 


2 
4 
6 
6 


8(4,4) 
15(4,4,4,3) 
23(4,4,3,5,4,3) 
23(4,4,3,5,4,3) 


2.00 

3.75 
5.75 
5.75 



Condition Bits Affected: 

S: Set if result is negative; reset otherwise 

Z: Set if result is zero; reset otherwise 

H: Reset 

P/V: Set if parity is even; reset otherwise 

N: Reset 

C: Data from Bit of source register 



170 



ROTATE AND SHIFT GROUP 



Example: 

If the contents of the Index Register IX are 1000H, and the contents of memory 
location 1003H are 



7 



5 



3 



1 



10 1110 



after the execution of 

SRA (IX+3H) 

the contents of memory location 1003H and the Carry Flag will be 

76543210 C 



i I i I o I i I i I l ooo 



SDI m 
I & eL™ III 



Shift Right Logical 



Operation: (ty | 7-QO K > I CY 

m 

Format: 

Mnemonic: SRL Operands: m 

The operand m is any of r, (HL), (IX + d) or (IY+ d), as defined for the 
analogous RLC instructions. These various possible opcode-operand 
combinations are specified as follows in the assembled object code: 



Object Code: 


















SRLr 


1 


1 








1 





1 


1 




























1 


1 


1 


r 


r 


r 




















SRL (HL) 


1 


1 








1 





1 


1 




























1 


1 


1 


1 


1 






CB 



CB 



3E 



171 



SERIES I EDITOR/ASSEMBLER 



SRL(IX+d) 



SRL(IY+d) 



1 1 1 1 1 1 1 

110 1110 1 

1 1 1 1 1 1 1 




1 1 1 1 1 1 1 

110 10 11 

1 1 1 1 1 1 1 




1 1 1 1 1 I 1 

dddddddd 

i i i i i i i 




II 

111110 

1 1 




1 1 1 1 1 1 1 

1111110 1 

1 1 I 1 1 1 1 




I 1 1 1 1 1 1 

110 10 11 

1 1 1 1 1 1 1 




1 1 1 1 1 1 1 

dddddddd 

i i i i i i i 




i I i i I 1 1 

111110 

II 



DD 



CB 



3E 



FD 



CB 



3E 



r identifies registers B, C, D, E, H, L or A specified as follows in the assembled 
object code fields above: 

Register r 

B 000 

C 001 

D 010 

E 011 

H 100 

L 101 

A 111 



Description: 

The contents of operand m are shifted right: the content of bit 7 is copied into 
bit 6; the content of bit 6 is copied into bit 5; this pattern is continued 
throughout the byte. The content of bit is copied into the Carry Flag, and bit 7 
is reset. Bit is the least significant bit. 



172 



ROTATE AND SHIFT GROUP 



Instruction 

SRLr 
SRL (HL) 
SRL(IX+d) 
SRL(IY+d) 



M 
Cycles 

2 
4 
6 



T States 

8(4,4,) 
15(4,4,4,3) 
23(4,4,3,5,4,3) 
23(4,4,3,5,4,3) 



Condition Bits Affected: 



S: Set if result is negative; reset otherwise 

Z: Set if result is zero; reset otherwise 

H: Reset 

P/V: Set if parity is even; reset otherwise 

N: Reset 

C: Data from Bit of source register 

Example: 

If the contents of register B are 
7 6 5 4 3 2 10 



10 1111 



4 MHz 

EX in (xs 

2.00 

3.75 
5.75 
5.75 



after the execution of 

SRL B 

the contents of register B and the Carry Flag will be 

7 6 5 4 3 2 10 C 



10 111 1 



Ri n 
L.LJ 



"^ 



Operation: A |74|30| |7 4|3 0| (HL) 



Format: 
Mnemonic: RLD 



Operands: 



Rotate Left Decimal 



173 



SERIES I EDITOR/ASSEMBLER 



Object Code: 



1 


1 


1 





1 


1 





1 







1 


1 





1 


1 


1 


1 



ED 



6F 



Description: 

The contents of the low order four bits (bits 3,2, 1 and 0) of the memory 
location (HL) are copied into the high order four bits (7, 6, 5 and 4) of that same 
memory location; the previous contents of those high order four bits are copied 
into the low order four bits of the Accumulator (register A), and the previous 
contents of the low order four bits of the Accumulator are copied into the low 
order four bits of memory location (HL). The contents of the high order bits of 
the Accumulator are unaffected. Note: (HL) means the memory location 
specified by the contents of the HL register pair. 

M cycles: 5 T states: 18(4,4,3,4,3) 4 MHz E.T.: 4.50 
Condition Bits Affected: 



S: Set if Ace. is negative after operation; reset otherwise 

Z: vSet if Ace. is zero after operation; reset otherwise 

H: Reset 

P/V: Set if parity of Ace. is even after operation; reset otherwise 

N: Reset 

C: Not affected 



Example: 

If the contents of the HL register pair are 5000H, and the contents of the 
Accumulator and memory location 5000H are 



7 6 5 4 3 



1 



11110 10 



Accumulator 



7 6 5 4 3 2 10 

(5000H) 



1 10 1 



174 



ROTATE AND SHIFT GROUP 



after the execution of 

RLD 

the contents of the Accumulator and memory location 5000H will be 

7 6 5 4 3 2 10 

Accumulator 



(5000H) 






1 


1 


1 








1 


1 


7 


6 


5 


4 


3 


2 


1 














1 


1 





1 






RRD 



^> 



Operation: A[74j30j 1741301 (HL) 



Rotate Right Decimal 



Format: 

Mnemonic: RRD Operands: 



Object Code: 










I I I 
1110 


1 


1 





1 




1 1 i 
110 

1 1 1 





1 


1 


1 



ED 



67 



Description: 

The contents of the low order four bits (bits 3, 2, 1 and 0) of memory location 
(HL) are copied into the low order four bits of the Accumulator (register A); the 
previous contents of the low order four bits of the Accumulator are copied into 
the high order four bits (7, 6, 5 and 4) of location (HL); and the previous 
contents of the high order four bits of (HL) are copied into the low order four 
bits of (HL). The contents of the high order bits of the Accumulator are 
unaffected. Note: (HL) means the memory location specified by the contents 
of the HL register pair. 

M cycles: 5 T states: 18(4,4,3,4,3) 4 MHz E.T.: 4.50 
Condition Bits Affected: 



175 



SERIES i EDITOR/ASSEMBLER 



es^ 



, ^iW; , ^:K 



:~ "'*,»■%!■„. ii'.MJ y;~ rn* ,.~.-r : .w^kS'z.si- *:&.'. "^: '>S; , J/a>^' l yjgS«'.'1'fBi 



S: Set if Ace. is negative after operation; reset otherwise 

Z: Set if Ace. is zero after operation; reset otherwise 

H: Reset 

P/V: Set if parity of Ace. is even after operation; reset otherwise 

N: Reset 

C: Not affected 



Example: 

If the contents of the HL register pair are 5000H, and the contents of the 
Accumulator and memory location 5000H are 



7 



4 3 



1 



1 














1 








7 


6 


5 


4 


3 


2 


1 











1 


















Accumulator 



______ (5000H) 

after the execution of 
RRD 

the contents of the Accumulator and memory location 5000H will be 
7 6 5 4 3 2 10 

Accumulator 



1 























7 


6 


5 


4 


3 


2 


1 








1 














1 






(5000H) 



176 



BIT SET, RESET AND TEST GROUP 



Bit Set, Reset and Test Group 
BIT b 3 r 

Operation: Z <J T^ 

Format: 

Mnemonic: BIT Operands: b, r 



BIT test 



Object ( 


>ode 












1 1 

i 








1 





1 


1 




1 

i 


b 


b 


b 


r 


r 


r 



CB 



Description: 

After the execution of this instruction, the Z flag in the F register will contain 
the complement of the indicated bit within the indicated register. Operands b 
and r are specified as follows in the assembled object code: 



Bit 








Tested 


b 


Register 


r 





000 


B 


000 


1 


001 


C 


001 


2 


010 


D 


010 


3 


011 


E 


011 


4 


100 


H 


100 


5 


101 


L 


101 


6 


110 


A 


111 


7 


111 







M cycles: 2 T states: 8(4,4) 4 MHz E.T. : 2. 



Condition Bits Affected: 



S: 


Unknown 


Z: 


Set if specified Bit is 0; reset otherwise 


H: 


Set 


P/V: 


Unknown 


N: 


Reset 


C: 


Not affected 



iJ^jiJi^fiiSl^pi^pft#^§SiP 



177 



SERIES I EDITOR/ASSEMBLER 



Example: 

If bit 2 in register B contains 0, after the execution of 

BIT 2, B 

the Z flag in the F register will contain 1, and bit 2 in register B will remain 
(Bit in register B is the least significant bit.) 



BIT b,(HL) 



Bit Test 



Operation: Z<0 (HL)(-, 

Format: 

Mnemonic: BIT Operands: b, (HL) 



Object Code: 



1 


1 








1 





1 


1 







1 


b 


b 


b 


1 


1 






CB 



Description: 

This instruction tests bit b in the memory location specified by the contents of 
the HL register pair and sets the Z flag accordingly. Operand b is specified as 
follows in the assembled object code: 



Bit 
Tested 


1 

2 
3 
4 
5 
6 
7 



001 
010 
011 
100 
101 
110 
111 



M cycles: 3 T states: 12(4,4,4) 4 MHz E.T.: 3.« 



Condition Bits Affected: 



178 



BIT SET, RESET AND TEST GROUP 



fnattjt.. «- .:»..i 



11 



'.~j?%~ "> .."* -^-^j 



'ZZZJ 



■ 



S: 


Unknown 


Z: 


Set if specified Bit is 0; reset otherwise 


H: 


Set 


P/V: 


Unknown 


H: 


Reset 


C: 


Not affected 



Example: 

If the HL register pair contains 444H, and bit 4 in the memory location 444H 
contains 1, after the execution of 

BIT 4,(HL) 

the Z flag in the F register will contain 0, and bit 4 in memory location 444H 
will still contain 1. (Bit in memory location 444H is the least significant bit.) 



BITb,(IX+d 



Bit Test 



Operation: Z <) (IX+ d)b 

Format: 

Mnemonic: BIT Operands: b, (IX+d) 



Object Code: 



1 


1 





1 


1 


1 





1 






1 


1 








1 





1 


1 






d 


d 


d 


d 


d 


d 


d 


d 









1 


b 


b 


b 


1 


1 






DD 



CB 



Description: 

After the execution of this instruction, the Z flag in the F register will contain 
the complement of the indicated bit within the contents of the memory location 
pointed to by the sum of the contents register pair IX (Index Register IX) and 
the two's complement displacement integer d. Operand b is specified as follows 
in the assembled object code. 



179 



SERIES I EDITOR/ASSEMBLER 



Bit 




Tested 


b 





000 


1 


001 


2 


010 


3 


011 


4 


100 


5 


101 


6 


110 


7 


111 



M cycles 


5 T states: 


20(4,4,3,5,4) 


4 MHz E.T. 


5 


Condition Bits Affected: 








S: 


Unknown 








Z: 


Set if specified 


Bit is 0; reset otherwise 




H: 


Set 








P/V: 


Unknown 








N: 


Reset 








C: 


Not affected 









Example: 

If the contents of Index Register IX are 2000H, and bit 6 in memory location 
2004H contains 1 , after the execution of 

BIT 6,(IX+4H) 

the Z flag in the F register will contain 0, and bit 6 in memory location 2004H 
will still contain 1. (Bit in memory location 2004H is the least significant bit.) 



BITb,(IY+d) 

Operation: Z<l(IY+d) b 

Format: 

Mnemonic: BIT Operands: b, (IY+d) 

Object Code: 

— I 1 1 1 1 

FD 

CB 



BIT Test 



1 


1 


1 


1 


1 


1 





1 






1 


1 








1 





1 


1 






d 


d 


d 


d 


d 


d 


d 


d 









1 


b 


b 


b 


1 


1 






180 



BIT SET, RESET AND TEST GROUP 



Description: 

After the execution of this instruction, the Z flag in the F register will contain 
the complement of the indicated bit within the contents of the memory location 
pointed to by the sum of the contents of register pair IY (Index Register IY) and 
the two's complement displacement integer d. Operand b is specified as follows 
in the assembled object code: 



Bit 










Tested 


b 











000 








1 


001 








2 


010 








3 


011 








4 


100 








5 


101 








6 


110 








7 


111 








M cycles 


: 5 T states: 


20(4,4,3,5,4) 


4MHzE.T.:5 


Condition Bits Affected: 








S: 


Unknown 








Z: 


Set if specified 


Bit is 0; 


reset otherwise 


H: 


Set 








P/V: 


Unknown 








N: 


Reset 








C: 


Not affected 









Example: 

If the contents of Index Register are 2000H, and bit 6 in memory location 
2004H contains 1, after the execution of 

BIT 6,(IY+4H) 

the Z flag in the F register still contain 0, and bit 6 in memory location 2004H 
will still contain 1. (Bit in memory location 2004H is the least significant bit.) 



SETbr 

Operation: P^l 



Format: 

Mnemonic: SET Operands: b, r 



181 



SERIES I EDITOR/ASSEMBLER 



E3 



Object Code: 





1 


1 








1 





1 


1 




1 


1 


b 


b 


b 


r 


r 


r 



CB 



Description: 

Bit b (any bit, 7 through 0) in register r (any of register B, C, D, E, H, L or A) 
is set. Operands b and r are specified as follows in the assembled object code: 



Tested 


b 


Register 


r 







000 


B 


000 




1 


001 


C 


001 




2 


010 


D 


010 




3 


011 


E 


011 




4 


100 


H 


100 




5 


101 


L 


101 




6 


110 


A 


111 




7 


111 








M cycles 


:2 


T states: 8(4 


,4) 


4MHzE.T.: 2 



Condition Bits Affected: None 

Example: 

After the execution of 

SET 4,A 

bit 4 in register A will be set. (Bit is the least significant bit.) 



Operation: (HL)^ 1 

Format: 

Mnemonic: SET Operands: b, (HL) 



182 



BIT SET, RESET AND TEST GROUP 



Object Code: 








I I 1 
110 


1 

I l 


1 


1 




1 1 1 
1 1 b b 

i i i 


1 

b 1 

i 


1 






CB 



Description: 

Bit b (any bit, 7 through 0) in the memory location addressed by the contents of 
register pair HL is set. Operand b is specified as follows in the assembled object 
code: 



Bit 




Tested 


b 





000 


1 


001 


2 


010 


3 


011 


4 


100 


5 


101 


6 


110 


7 


111 



M cycles: 4 T states: 15(4,4,4,3) 4 MHz E.T.: 3.75 
Condition Bits Affected: None 

Example: 

If the contents of the HL register pair are 3000H, after the execution of 

SET 4,(HL) 

bit 4 in memory location 3000H will be 1. (Bit in memory location 3000H 
is the least significant bit.) 

SETb,(IX+d) 

Operation: (IX+d) b <]1 

Format: 

Mnemonic: SET Operands: b, (IX+d) 



183 



SERI ES 1 EDITOR/AS SEMBLER 



Object Code: 



1 


1 





1 


1 


1 





1 








1 


1 








1 





1 


1 








d 


d 


d 


d 


d 


d 


d 


d 








1 


1 


b 


b 


b 


1 


1 






DD 



CB 



Description: 

Bit b (any bit, 7 through 0) in the memory location addressed by the sum of the 
contents of the IX register pair (Index Register IX) and the two's complement 
integer d is set. Operand b is specified as follows in the assembled object code: 



Bit 




Tested 


b 





000 


1 


001 


2 


010 


3 


011 


4 


100 


5 


101 


6 


110 


7 


111 



M cycles: 6 T states: 23(4,4,3,5,4,3) 4 MHz E.T.: 5.75 
Condition Bits Affected: None 

Example: 

If the contents of Index Register are 2000H, after the execution of 

SET 0,(IX+3H) 

bit in memory location 2003H will be 1. (Bit in memory location 2003H 
is the least significant bit.) 



184 



BIT SET, RESET AND TEST GROUP 



SETb,(IY+d) 

Operation: (IY+d) b <l1 

Format: 

Mnemonic: SET Operands: b, (lY+d) 



Object Code: 



I I I I I I l 

1111110 1 

1 1 1 1 1 1 ] 




1 1 1 1 1 1 1 

110 10 11 

1 1 1 1 1 1 1 




1 1 1 I 1 1 1 

dddddddd 

i i i i i i i 




1 I I I I i I 
1 1 b b b 1 1 



FD 



CB 



Description: 

Bit b (any bit, 7 through 0) in the memory location addressed by the sum of the 
contents of the IY register pair (Index Register IY) and the two's complement 
displacement d is set. Operand b is specified as follows in the assembled object 
code: 



Bit 




Tested 


b 





000 


1 


001 


2 


010 


3 


011 


4 


100 


5 


101 


6 


110 


7 


111 



M cycles: 6 T states: 23(4,4,3,5,4,3) 4 MHz E.T.: 5.75 



Condition Bits Affected: None 



185 



SERIES I EDITOR/ASSEMBLER 



Example: 

If the contents of Index Register IY are 2000H, after the execution of 

SET 0,(IY+3H) 

bit in memory location 2003H will be 1 . (Bit in memory location 2003H 
is the least significant bit.) 



RES b,m 

Operation: S^O 



RESet 



Format: 

Mnemonic: RES Operands: b, m 

Operand b is any bit (7 through 0) of the contents of the m operand, (any of r, 
(HL), (1X+ d) or (IY+ d) as defined for the analogous SET instructions. These 
various possible opcode-operand combinations are assembled as follows in the 
object code: 



Object Code: 



RES b, r 



RES b, (HL) 



RESb, (IX +d) 



1 1 1 1 1 1 1 

110 10 11 

1 1 1 1 1 1 I 




1 1 1 1 1 1 1 

lObbbrrr 

i i i i i i i 




l l l l l l I 
110 10 11 




1 b b b 1 10 




1 1 1 1 1 1 I 

110 1110 1 

1 1 1 1 1 1 1 




1 1 1 1 1 1 1 

110 10 11 

1 1 1 1 1 I 1 




1 1 1 1 1 1 1 

dddddddd 

i i i i i i i 




1 1 1 ! ! 1 1 

1 b b b 1 10 

l l l l l l l 



CB 



CB 



DD 



CB 



186 



BIT SET, RESET AND TEST GROUP 



RESb, (IY+d) 



1 


1 


1 


1 


1 


1 





1 












1 


1 








1 





1 


1 














d 


d 


d 


d 


d 

_ 


d 


d 


d 












1 





b 


b 


b 


1 


1 






FD 



CB 



Bit 










Reset b 


Register 


r 




000 


B 




000 




1 001 


C 




001 




2 010 


D 




010 




3 011 


E 




011 




4 100 


H 




100 




5 101 


L 




101 




6 110 


A 




111 




7 111 










Description: 










Bit b in operand m is reset. 










M 




4 MHz 


Instruction 


Cycles T States 


E.T. in (xs 


RESr 




4 


8(4,4) 


2.00 


RES (HL) 




4 


15(4,4,4,3) 


3.75 


RES(IX+d) 




6 


23(4,4,3,5,4,3) 


5.75 


RES (IY+d) 




6 


23(4,4,3,5,4,3) 


5.75 



Condition Bits Affected: None 

Example 1: 

After the execution of 

RES 6,D (object code CB, B2H) 

bit 6 in register D will be reset. (Bit in register D is the least significant bit.) 

Example 2: 

If HL contains 7000H and address 7000H contains FFH, after 

RES 0,(HL) 

address 7000H will contain FEH. 



187 



JUMP GROUP 



Jump Group 



JPnn 



JumP 



Operation: PC <1 nn 

Format: 

Mnemonic: JP Operands: nn 



Object Code: 



1 


1 














1 


1 




n 


n 


n 


n 


n 


n 


n 


n 




n 


n 


n 


n 


n 


n 


n 


n 



C3 



Note: The first operand in this assembled object code is the low order byte of a 

2-byte address. 

Description: 

Operand nn is loaded into register pair PC (Program Counter) and points to the 
address of the next program instruction to be executed. 

M cycles: 3 T states: 10(4,3,3) 4 MHz E.T.: 2.50 
Condition Bits Affected: None 

Example: 

JP 50A1 

This instruction will cause the program to jump to the instruction at 50A1H by 
loading the number 50A1H into the PC register. 



189 



SERIES ! EDITOR/ASSEMBLER 



P ec,nn 

Operation: IF CC TRUE, PC<mn 

Format: 

Mnemonic: JP Operands: cc, nn 



JumP 



Obj. 


ect C 


"ode 


J 










1 


1 


cc 


cc 


cc 





1 











n 


n 


n 


n 


n 


n 


n 


n 








n 


n 


n 


n 


n 


n 


n 


n 



Note: The first n operand in this assembled object code is the low order byte of a 
2-byte memory address. 

Description: 

If condition cc is true, the instruction loads operand nn into register pair PC 
(Program Counter), and the program continues with the instruction beginning at 
address nn. If condition cc is false, the Program Counter is incremented as 
usual, and the program continues with the next sequential instruction. Condition 
cc is programmed as one of eight status bits which correspond to condition bits 
in the Flag Register (register F). These eight status bits are defined in the table 
below, which also specifies the corresponding cc bit fields in the assembled 
object code. 







Relevant 


cc 


Condition 


Flag 


000 


NZ non-zero 


Z ( = 0) 


001 


Z zero 


Z (=1) 


010 


NC no-carry 


C ( = 0) 


011 


C carry 


C (=1) 


100 


PO parity odd 


P/V( = 0) 


101 


PE parity even 


P/V(=l) 


110 


P sign positive 


S ( = 0) 


111 


M sign negative 


S (=1) 


M cy 


cles: 3 T states: 


10(4,3,3) 4MHzE.T. 



2.50 



Condition Bits Affected: None 



■HI 



190 



JUMP GROUP 



Example: 

If the Carry Flag (C flag in the F register) is set and the contents of address 1520 
are 03H, after the execution of 

JP C.1520H 

the Program Counter will contain 1520H, and on the next machine cycle the 
CPU will fetch from address 1520H the byte 03H. 

JH G Jump Relative 

Operation: PC ^! PC + e 

Format: 

Mnemonic: JR Operands: e 

Object Code: 

18 












1 


1 













e-2 


e-2 


e-2 


e-2 


e-2 


e-2 


e-2 


e-2 



Description: 

This instruction provides for unconditional branching to other segments of a 
program. The value of the displacement e is added to the Program Counter (PC) 
and the next instruction is fetched from the location designated by the new 
contents of the PC. This jump as measured from the address of the instruction 
opcode has a range of - 126 to + 129 bytes. The assembler automatically 
adjusts for the twice incremented PC. 

M cycles: 3 T states: 12(4,3,5) 4 MHz E.T.: 3.00 
Condition Bits Affected: None 

Example 1: 

To jump forward five locations from address 480, the following assembly 
language statement is used: 

JR $ + 5 

The resulting object code and final PC value is shown below: 



191 



SERIES I EDITOR/ASSEMBLER 



Location Instruction 

480 18 

481 03 

482 — PC before jump 

483 — 

484 — 

485 <0 PC after jump 

Note: when using an assembler, $ + 5 used above would normally be replaced 
by a label. 

Example 2: 

This program will skip around the NOP instruction. 

START JR, END 

NOP 
END — 



JR C 3 G Jump Relative 

Operation: If C = 0, Continue 

lfC = 1,PC<iPC + e 

Format: 

Mnemonic: JR Operands: C, e 



38 



Object C 


]ode 












I 



I 


1 


1 


1 













I 

e-2 e-2 

i 


e-2 


e-2 


e-2 


e-2 


e-2 


e-2 



Description: 

This instruction provides for conditional branching to other segments of a 
program depending on the results of a test on the Carry Flag. If the flag is equal 
to a ' 1 ,' the value of the displacement e is added to the Program Counter (PC) 
and the next instruction is fetched from the location designated by the new 
contents of the PC. The jump as measured from the address of the instruction 
opcode has a range of — 126 to + 129 bytes. The assembler automatically 
adjusts for the twice incremented PC. 

If the flag is equal to a '0,' the next instruction to be executed is taken from the 
location following this instruction. 



192 



JUMP GROUP 



If condition is met: 

M cycles: 3 T states: 12(4,3,5) 4 MHz E.T.: 3.00 

If condition is not met: 

M cycles: 2 T states: 7(4,3) 4 MHz E.T.: 1.75 

Condition Bits Affected: None 

Example: 

The Cany Flag is set and it is required to jump back four locations from 480. 
The assembly language statement is: 

JR C, $-4 

The resulting object code and final PC value is shown below: 

Location Instruction 

47C PC after jump 

47D — 

47E — 

47F — 

480 38 

481 FA (two 's complement - 6) 

482 <l PC before jump 



JR NC 5 e 

Operation: If C = 1 , Continue 

lfC = 0,PC<iPC + e 

Format: 

Mnemonic: JR Operands: NC, e 

Object Code: 









1 


1 















e-2 e-2 e-2 e-2 e-2 e-2 e-2 e-2 

I I I I I I L__ 



30 



Jump Relative 



Description: 

This instruction provides for conditional branching to other segments of a 
program depending on the results of a test on the Carry Flag. If the flag is equal 
to '0,' the value of the displacement e is added to the Program Counter (PC) and 



193 



SERIES I EDITOR/ASSEMBLER 



the next instruction is fetched from the location designated by the new contents 
of the PC. The jump as measured from the address of the instruction opcode has 
a range of - 126 to + 129 bytes. The assembler automatically adjusts for the 
twice incremented PC. 

If the flag is equal to a '1,' the next instruction to be executed is taken from the 
location following this instruction. 

If the condition is met: 

M cycles: 3 T states: 12(4,3,5) 4 MHz E.T.: 3.00 

If the condition is not met: 

M cycles: 7 T states: 7(4,3) 4 MHz E.T.: 1.75 

Condition Bits Affected: None 

Example: 

The Carry Flag is reset and it is required to repeat the jump instruction. 
The assembly language statement is: 

JR NC,$ 

The resulting object code and PC after the jump are shown below: 

Location Instruction 

480 300 PC after jump 

48 1 FD (two's complement - 2) 

482 — <l PC before jump 

Note: this instruction would cause an infinite loop in the program. 



J_ 



Jump Relative 



Operation: Z = 0, Continue 

lfZ = 1,PC<iPC + e 

Format: 

Mnemonic: JR Operands: Z, e 



Object Code: 












I i i 

1 

i i i 





1 













e-2 e-2 e-2 

i i i 


e-2 


e-2 


e-2 


e-2 


e-2 



28 



194 



JUMP GROUP 



Description: 

This instruction provides for conditional branching to other segments of a 
program depending on the results of a test on the Zero Flag. If the flag is equal 
to a ' 1,' the value of the displacement e is added to the Program Counter (PC) 
and the next instruction is fetched from the location designated by the new 
contents of the PC. The jump as measured from the address of the instruction 
opcode has a range of - 126 to + 129 bytes. The assembler automatically 
adjusts for the twice incremented PC. 

If the Zero Flag is equal to a '0,' the next instruction to be executed is taken 
from the location following this instruction. 

If the condition is met: 

M cycles: 3 T states: 12(4,3,5) 4 MHz E.T.: 3.00 

If the condition is not met: 

M cycles: 2 T states: 7(4,3) 4 MHz E.T.: 1.75 

Condition Bits Affected: None 

Example: 

The Zero Flag is set and it is required to jump forward five locations from 
address 300. The following assembly language statement is used: 

JR Z, $ + 5 

The resulting object code and final PC value is shown below: 



Location 


Instruction 




300 


28 




301 


03 




302 


— OPCbefor 


e jump 


303 


— 




304 


— 




305 


— <] PC after 


jump 



JR NZ.G Jump Relative 



Operation: If Z = 1 , Continue 

lfZ = 0,PC<iPC + e 

Format: 

Mnemonic: JR Operands: NZ, e 



195 



SERIES I EDITOR/ASSEMBLER 



Object Code: 









1 



















e-2 


e-2 


e-2 


e-2 


e-2 


e-2 


e-2 


e-2 



20 



Description: 

This instruction provides for conditional branching to other segments of a 
program depending on the results of a test on the Zero Flag. If the flag is equal 
to a '0,' the value of the displacement e is added to the Program Counter (PC) 
and the next instruction is fetched from the location designated by the new 
contents of the PC. The jump as measured from the address of the instruction 
opcode has a range of - 126 to + 129 bytes. The assembler automatically 
adjusts for the twice incremented PC. 

If the Zero Flag is equal to a '1,' the next instruction to be executed is taken 
from the location following this instruction. 

If the condition is met: 

M cycles: 3 T states: 12(4,3,5) 4 MHz E.T.: 3.00 

If the condition is not met: 

M cycles: 2 T states: 7(4,3) 4 MHz E.T.: 1.75 

Condition Bits Affected: None 

Example: 

The Zero Flag is reset and it is required to jump back four locations from 480. 
The assembly language statement is: 

JR NZ, $-4 

The resulting object code and final PC value is shown below: 

Location Instruction 

47C <i PC after jump 

47D — 

47E — 

47F — 

480 20 

48 1 FA (two 's complement - 6) 

482 — <l PC before jump 



196 



JUMP GROUP 



Jr (r"IL) Jump 

Operation: PC(lHL 



Format: 

Mnemonic: JP Operands: (HL) 

Object Code: 

"1 T I i I 1 1 1 

[110 10 1 E9 



Description: 

The Program Counter (register pair PC) is loaded with the contents of the HL 
register pair. The next instruction is fetched from the location designated by the 
new contents of the PC. 

M cycles: 1 T states: 4 4 MHz E.T.: 1.00 
Condition Bits Affected: None 

Example 1: 

If the contents of the Program Counter are 1000H and the contents of the HL 
register pair are 4800H, after the execution of 

JP (HL) 

the contents of the Program Counter will be 4800H. 

The program will jump to the instruction at address 4800H. 

Example 2: 

A typical software routine which uses JP (HL) is a jump table lookup program. 
Assume that n 16-bit addresses are listed in consecutive bytes of memory 
starting at address TBL. Also assume that the Accumulator contains a number 
from to n-1 representing the routine to be jumped to. 

LD HL, TBL ; HL points to the first byte in the table. 

ADD A, A ; double A 

LD DE, 

LD E, A 

ADD HL, DE ; if A originally contained 5, then HL now points to the 

5th address in the table 

LD E, (HL) 

INC HL 

LD D, (HL) ; DE now contains the 5th address of the table 

LD HL, DE ; HL now contains the 5th address of the table 

JP (HL) 



197 



SERIES I EDITOR/ASSEMBLER 



JP (IX) 

Operation: PC <0 IX 

Format: 

Mnemonic: JP Operands: (IX) 



JumP 



Object Code: 



1 


1 





1 


1 


1 





1 




1 


1 


1 





1 








1 



DD 



E9 



Description: 

The Program Counter (register pair PC) is loaded with the contents of the 
IX Register Pair (Index Register IX). The next instruction is fetched from the 
location designated by the new contents of the PC. 

M cycles: 2 T states: 8(4,4) 4 MHz E.T.: 2.00 
Condition Bits Affected: None 

Example: 

If the contents of the Program Counter are 1000H, and the contents of the 
IX Register Pair are 4800H, after the execution of 

JP (IX) 

the contents of the Program Counter will be 4800H. 



JP (IY) 

Operation: PC <l I Y 

Format: 

Mnemonic: JP Operands: (IY) 



JumP 



Object Code: 



198 



JUMP GROUP 



1 


1 


1 


1 


1 


1 





1 




1 


1 


1 





1 








1 



FD 



E9 



Description: 

The Program Counter (register pair PC) is loaded with the contents of the 
IY Register Pair (Index Register IY). The next instruction is fetched from the 
location designated by the new contents of the PC. 

M cycles: 2 T states: 8(4,4) 4 MHz E.T.: 2.00 
Condition Bits Affected: None 

Example: 

If the contents of the Program Counter are 1000H and the contents of the 
IY Register Pair are 4800H, after the execution of 

JP (IY) 

the contents of the Program Counter will be 4800H. 



DJNZe 



Decrement Jump Not Zero 



Operation: 

Format: 
Mnemonic: DJNZ 



Operands: e 



Object Code: 












1 1 1 



1 1 1 


1 
















1 I 1 
e-2 e-2 e-2 


e-2 


e-2 


e-2 


e-2 


e-2 



10 



Description: 

The instruction is similar to the conditional jump instructions except that a 
register value is used to determine branching. The B register is decremented 
and if a non zero value remains, the value of the displacement e is added to 
the Program Counter (PC) . The next instruction is fetched from the location 



B 



199 



SERIES I EDITOR/ASSEMBLER 



designated by the new contents of the PC. The jump is measured from 
the address of the instruction opcode has a range of — 126 to +129 bytes. 
The assembler automatically adjusts for the twice incremented PC. 

If the result of decrementing leaves B with a zero value, the next instruction 
to be executed is taken from the location following this instruction. 

IfB*0: 

M cycles: 3 T states: 13(5,3,5) 4 MHz E.T.: 3.25 

IfB = 0: 

M cycles: 2 T states: 8(5,3) 4 MHz E.T.: 2.00 



Condition Bits Affected: None 



Example: 



A typical software routine is used to demonstrate the use of the DJNZ 
instruction. This routine moves a line from an input buffer (INBUF) to an output 
buffer (OUTBUF). It moves the bytes until it finds a carriage return, or until it 
has moved 80 bytes, whichever occurs first. 



LOOP: 



LD 


B,80 


Set up counter 


LD 


HL, Inbuf 


Set up pointers 


LD 


DE, Outbuf 




LD 


A, (HL) 


Get next byte from 
input buffer 


LD 


(DE), A 


Store in output buffer 


CP 


0DH 


Is it a CR? 


JPv 


Z, DONE 


Yes finished 


INC 


HL 


Increment pointers 


INC 


DE 




DJNZ 


LOOP 


Loop back if 80 
bytes have not 
been moved 



DONE: 



200 



CALL AND RETURN GROUP 



Call and Return Group 
CALL nn 

Operation: (SP - 1 )<l PC H , (SP - 2)<l PC L) PC <1 nn 

Format: 

Mnemonic: CALL Operands: nn 



Object Code: 










110 

i i i 


1 


1 





1 




1 I I 

n n n n 

i i i 


n 


n 


n 


n 




n n n n 

i i i 


n 


n 


n 


n 



CD 



Note: The first of the two n operands in the assembled object code above is the 
least significant byte of a two-byte memory address. 

Description: 

After pushing the current contents of the Program Counter (PC) onto the top of 
the external memory stack, the operands nn are loaded into PC to point to the 
address in memory where the first opcode of a subroutine is to be fetched. (At 
the end of the subroutine, a RETurn instruction can be used to return to the 
original program flow by popping the top of the stack back into PC.) The push 
is accomplished by first decrementing the current contents of the Stack Pointer 
(register pair SP), loading the high-order byte of the PC contents into the 
memory address now pointed to by the SP; then decrementing SP again, and 
loading the low-order byte of the PC contents into the top of stack. Note: 
Because this is a three-byte instruction, the Program Counter will have been 
incremented by three before the push is executed. 

M cycles: 5 T states: 17(4,3,4,3,3) 4 MHz E.T.: 4.25 
Condition Bits Affected: None 

Example: 

If the contents of the Program Counter are 1A47H, the contents of the Stack 
Pointer are 3002H, and memory locations have the contents: 



201 



SERIES I EDITOR/ASSEMBLER 



Location Contents 

1A47H CDH 

1A48H 35H 

1A49H 21H 

then if an instruction fetch sequence begins, the three-byte instruction CD3521H 
will be fetched to the CPU for execution. The mnemonic equivalent of this is 

CALL 2135H 

After the execution of this instruction, the contents of memory address 300 1H 
will be 1AH, the contents of address 3000H will be 4AH, the contents of the 
Stack Pointer will be 3000H, and the contents of the Program Counter will be 
2135H, pointing to the address of the first opcode of the subroutine now to be 
executed. 

Before: 



Stack Pointer 


Address 


Stack 


3002 


3002 


50 




3003 


IB 




3004 


3C 


Program Counter 






1A47 






After CALL 


2135H: 




Stack Pointer 


Address 


Stack 


3000 


3000 


4A 




3001 


1A 




3002 


50 




3003 


IB 


Program Counter 






2135 







w/*L.L. C/OjiSn 



Operation: IF CC TRUE: (SP - 1)<] PC H 

(SP-2)<]PC L , PCOnn 

Format: 

Mnemonic: CALL Operands: cc, nn 



202 



CALL AND RETURN GROUP 



Object Code: 



1 


1 


cc 


cc 


cc 


1 










n 


n 


1 

n 

I 


n 


n 


n 


n 


n 




n 


n 


1 

n 

1 


n 


n 


n 


n 


n 



Note: The first of the two n operands in the assembled object code above is the 
least significant byte of the two-byte memory address. 

Description: 

If condition cc is true, this instruction pushes the current contents of the 
Program Counter (PC) onto the top of the external memory stack, then loads 
the operands nn into PC to point to the address in memory where the first 
opcode of a subroutine is to be fetched. (At the end of the subroutine, a RETurn 
instruction can be used to return to the original program flow by popping the top 
of the stack back into PC.) If condition cc is false, the Program Counter is 
incremented as usual, and the program continues with the next sequential 
instruction. The stack push is accomplished by first decrementing the current 
contents of the Stack Pointer (SP), loading the high-order byte of the PC 
contents into the memory address now pointed to by SP, then decrementing 
SP again, and loading the low-order byte of the PC contents into the top of the 
stack. Note: Because this is a three-byte instruction, the Program Counter will 
have been incremented by three before the push is executed. Condition cc is 
programmed as one of eight status bits which corresponds to condition bits in 
the Flag Register (register F). Those eight status bits are defined in the table 
below, which also specifies the corresponding cc bit fields in the assembled 
object code: 



Relevant 
cc Condition Flag 

000 NZ non-zero Z ( = 0) 

001 Zzero Z (=1) 

010 NC non-carry C ( = 0) 

011 C carry C (=1) 

100 PO parity odd P/V( = 0) 

101 PE parity even P/ V ( = 1 ) 

110 P sign positive S ( = 0) 

111 M sign negative S (=1) 



203 



SERIES I EDITOR/ASSEMBLER 



If cc is true: 

M cycles: 5 T states: 17(4,3,4,3,3) 4 MHz E.T.: 4.25 

If cc is false: 

M cycles: 3 T states: 10(4,3,3) 4 MHz E.T.: 2.50 

Condition Bits Affected: None 

Example: 

If the C Flag in the F register is reset, the contents of the Program Counter are 
1A47H, the contents of the Stack Pointer are 3002H, and memory locations 
have the contents: 

Location Contents 

1A47H D4H 

1A48H 35H 

1A49H 21H 

then if an instruction fetch sequence begins, the three-byte instruction D43521H 
will be fetched to the CPU for execution. The mnemonic equivalent of this is 

CALL NC, 2135H 

After the execution of this instruction, the contents of memory address 300 1H 
will be 1AH, the contents of address 3000H will be 4AH, the contents of the 
Stack Pointer will be 3000H, and the contents of the Program Counter will be 
21.35H, pointing to the address of the first opcode of the subroutine now to be 
executed. 



Rr" 1 



RETum 

Operation: PC L <l(SP), PC H <l(SP + 1) 

Format: 

Mnemonic: RET Operands: 

Object Code: 

I I I I 1 

C9 



1 


1 








1 








1 



Description: 

Control is returned to the original program flow by popping the previous 
contents of the Program Counter (PC) off the top of the external memory stack, 
where they were pushed by the CALL instruction. This is accomplished by first 
loading the low-order byte of the PC with the contents of the memory address 



204 



CALL AND RETURN GROUP 



pointed to by the Stack Pointer (SP), then incrementing the SP and loading the 
high-order byte of the PC with the contents of the memory address now pointed 
to by the SP. (The SP is now incremented a second time.) On the following 
machine cycle the CPU will fetch the next program opcode from the location in 
memory now pointed to by the PC. 

M cycles: 3 T states: 10(4,3,3) 4 MHz E.T.: 2.50 
Condition Bits Affected: None 

Example: 

If the contents of the Program Counter are 3535H, the contents of the Stack 
Pointer are 2000H, the contents of memory location 2000H are B5H, and the 
contents of memory location 2001H are 18H, then after the execution of 

RET 

the contents of the Stack Pointer will be 2002H and the contents of the Program 
Counter will be 18B5H, pointing to the address of the next program opcode to 
be fetched. 

Before: 



Program Counter 


Address 


Stack 


3535 


2000 


B5 




2001 


18 




2002 


2E 




2003 


30 


Stack Pointer 






2000 






After RET: 






Program Counter 


Address 


Stack 


18B5 


2002 


2E 




2003 


30 


Stack Pointer 






2002 







RET CC RETurn 

Operation: IF cc TRUE: PCl^SP), PC H <l(SP + 1) 

Format: 

Mnemonic: RET Operands: cc 



205 



SERIES I EDITOR/ASSEMBLER 



Object Code: 



1 


1 


1 

cc 


cc 


cc 












Description: 

If condition cc is true, control is returned to the original program flow by 
popping the previous contents of the Program Counter (PC) off the top of the 
external memory stack, where they were pushed by the CALL instruction. This 
is accomplished by first loading the low-order byte of the PC with the contents 
of the memory address pointed to by the Stack Pointer (SP), then incrementing 
the SP, and loading the high-order byte of the PC with the contents of the 
memory address now pointed to by the SP. (The SP is now incremented a 
second time.) On the following machine cycle the CPU will fetch the next 
program opcode from the location in memory now pointed to by the PC. If 
condition cc is false, the PC is simply incremented as usual, and the program 
continues with the next sequential instruction. Condition cc is programmed as 
one of eight status bits which correspond to condition bits in the Flag Register 
F). These eight status bits are defined in the table below, which also specifies 
the corresponding cc bit fields in the assembled object code. 

Relevant 
cc Condition Flag 

000 NZ non-zero Z ( = 0) 

001 Zzero Z (=1) 

010 NC non-carry C ( = 0) 

011 C carry C (=1) 

100 PO parity odd P/V( = 0) 

101 PE parity even P/V(=l) 

110 P sign positive S ( = 0) 

111 M sign negative S ( = 1 ) 

If cc is true: 

M cycles: 3 T states: 1 1(5,3,3) 4 MHz E.T.: 2.75 

If cc is false: 

M cycles: 1 T states: 5 4 MHz E.T.: 1.25 

Condition Bits Affected: None 

Example: 

If the S flag in the F register is set, the contents of the Program Counter are 
3535H, the contents of the Stack Pointer are 2000H, the contents of memory 
location 2000H are B5H, and the contents of memory location 2001H are 18H, 
then after the execution of 

RET M 



206 



CALL AND RETURN GROUP 



the contents of the Stack Pointer will be 2002H and the contents of the Program 
Counter will be 18B5H, pointing to the address of the next program opcode to 
be fetched. 



RETI 



Operation: Return from interrupt 

Format: 

Mnemonic: RETI Operands: 

Object Code: 



1 


1 


1 





1 


1 





1 







1 








1 


1 





1 



ED 



4D 



Description: 

This instruction is used at the end of an interrupt service routine to: 

1 . Restore the contents of the Program Counter (PC) (analogous to the RET 
instruction). 

2. To signal an I/O device that the interrupt routine has been completed. The 
RETI instruction facilitates the nesting of interrupts, allowing higher priority 
devices to suspend service of lower priority service routines. This instruction 
also resets the IFF1 and IFF2 flip flops. 

M cycles: 4 T states: 14(4,4,3,3) 4 MHz E.T.: 3.50 
Condition Bits Affected: None 

Example: 

Given: Two interrupting devices, A and B, connected in a daisy chain 
configuration with A having a higher priority than B . 



+ 



INT 



A 



B 



-IEI IEO 




IEI IEO 









B generates an interrupt and is acknowledged. (The interrupt enable out, IEO, 
of B goes low, blocking any lower priority devices from interrupting while B is 
being serviced). Then A generates an interrupt, suspending service of B. (The 



— 



207 



SERIES I EDITOR/ASSEMBLER 



Object Code: 






III! 

1110 1 

1 1 1 1 


1 
1 

1 


1 




1 1 1 1 

10 

1 1 1 1 


1 
1 

1 


1 



IEO of A goes 'low' indicating that a higher priority device is being serviced.) 
The A routine is completed and a RETI is issued resetting the IEO of A, 
allowing the B routine to continue. A second RETI is issued on completion of 
the B routine and the IEO of B is reset (high), allowing lower priority devices 
interrupt access. 

RCTM 
1 1 IM 

Operation: Return from non maskable interrupt 

Format: 

Mnemonic: RETN Operands: 



ED 



45 



Description: 

Used at the end of a service routine for a non maskable interrupt, this instruction 
executes an unconditional return which functions identically to the RET 
instruction. That is, the previously stored contents of the Program Counter (PC) 
are popped off the top of the external memory stack; the low-order byte of PC is 
loaded with the contents of the memory location pointed to by the Stack Pointer 
(SP), SP is incremented, the high-order byte of PC is loaded with the contents 
of the memory location now pointed to by SP, and SP is incremented again. 
Control is now returned to the original program flow: on the following machine 
cycle the CPU will fetch the next opcode from the location in memory now 
pointed to by the PC. Also the state of IFF2 is copied back into IFF1 to the state 
it had prior to the acceptance of the NMI. 

M cycles: 4 T states: 14(4,4,3,3) 4 MHz E.T.: 3.50 
Condition Bits Affected: None 

Example: 

If the contents of the Stack Pointer are 1000H and the contents of the Program 
Counter are 1A45H when a non maskable interrupt (NMI) signal is received, the 
CPU will ignore the next instruction and will instead restart to memory address 
0066H. That is, the current Program Counter contents of 1A45H will be pushed 
onto the external stack address of 0FFFH and 0FFEH, high order byte first, and 



208 



CALL AND RETURN GROUP 



0066H will be loaded onto the Program Counter. That address begins an 
interrupt service routine which ends with RETN instruction. Upon the execution 
of RETN, the former Program Counter contents are popped off the external 
memory stack, low-order first, resulting in a Stack Pointer contents again of 
1000H. The program flow continues where it left off with an opcode fetch to 
address 1A45H. 



bl P ReSTart 

Operation: (SP - 1) PC H , (SP - 2)<l PC L , PC H O, PC L <] P 

Format: 

Mnemonic: RST Operands: P 

Object Code: 



] ! ! ! ! ! ! 

1 1 t t t 1 1 1 

l I I I I I I 



Description: 

The current Program Counter (PC) contents are pushed onto the external 
memory stack, and the page zero memory location given by operand p is loaded 
into the PC. Program execution then begins with the opcode in the address now 
pointed to by PC. The push is performed by first decrementing the contents of 
the Stack Pointer (SP), loading the high-order byte of PC into the memory 
address now pointed to by SP, decrementing SP again, and loading the low- 
order byte of PC into the address now pointed to by SP. The ReSTart instruction 
allows for a Call to a subroutine at one of eight addresses as shown in the table 
below. The operand p is assembled into the object code using the t column of 
the table. Note: Since all addresses are in page zero of memory, the high order 
byte of PC is loaded with 00H. The number selected from the "p" column of 
the table is loaded into the low-order byte of PC. 

At the end of the subroutine a RETurn instruction can be used to return to the 
original program by popping the top of the stack back into PC. 



p 


t 


00H 


000 


08H 


001 


10H 


010 


18H 


011 


20H 


100 


28H 


101 


30H 


110 


38H 


111 



M cycles: 3 T states: 11(5,3,3) 4 MHz E.T.: 2.75 



209 



SERIES I EDITOR/ASSEMBLER 



Example: 

If the contents of the Program Counter are 15B3H, after the execution of 

RST 18H (Object code 11011111) 

the PC will contain 0018H, as the address of the next opcode to be fetched, and 
the top number on the stack will be 15B3H. 



210 



INPUT AND OUTPUT GROUP 



Input and Output Group 



IN A,(n) 

Operation: A <l(n) 



INput 



Format: 

Mnemonic: IN Operands: A, (n) 

Object Code: 



1 


1 





1 


1 





1 


1 




n 


n 


n 


n 


n 


n 


n 


n 



DB 



Description: 

The number of the input port is n. Data is input to register A. The operand n is 
placed on the bottom half (A0 through A7) of the address bus to select the I/O 
device at one of 256 possible ports. The contents of the Accumulator also 
appear on the top half (A8 through A 15) of the address bus at this time. Then 
one byte from the selected port is placed on the data bus and written into the 
Accumulator (register A) in the CPU. 

M cycles: 3 T states: 11(4,3,4) 4 MHz E.T.: 2.75 
Condition Bits Affected: None 

Example: 

If the contents of the Accumulator are 23H and the byte 7BH is available at the 
peripheral device mapped to I/O port address 01H, then after the execution of 

IN A,(01H) 

the Accumulator will contain 7BH. 



211 



SERIES I EDITOR/ASSEMBLER 



IN r,(C) 



INput 



Operation: f<)(C) 

Format: 

Mnemonic: IN Operands: r, (C) 

Object Code: 



1 


1 


1 





1 


1 
1 

I 





1 







1 


1" 


r 


r 


1 


1 









ED 



Description: 

Register C contains the number of the input port. Data is input to register r. 
The contents of register C are placed on the bottom half (A0 through A7) of the 
address bus to select the I/O device at one of 256 possible ports. The contents of 
Register B are placed on the top half (A8 through A 15) of the address bus at this 
time. Then one byte from the selected port is placed on the data bus and written 
into register r in the CPU. Register r identifies any of the CPU registers shown 
in the following table, which also shows the corresponding three-bit "r" field 
for each. The flags will be affected, checking the input data. 



Register 


r 


B 


000 


C 


001 


D 


010 


E 


011 


H 


100 


L 


101 


A 


111 


M cycles: 


3 T states: 12(4,4,4) 4 MHz E.T.: 3 


Condition Bits Affected: 


S: 


Set if input data is negative; reset otherwise 


Z: 


Set if input data is zero; reset otherwise 


H: 


Reset 


P/V: 


Set if parity is even; reset otherwise 


N: 


Reset 


C: 


Not affected 



212 



INPUT AND OUTPUT GROUP 



Example: 

If the contents of register C are 07H, the contents of register B are 10H, and the 
byte 7BH is available at the peripheral device mapped to I/O port address 07H, 
then after the execution of 

IN D,(C) 

register D will contain 7BH 

A typical use of the IN r, (C) instruction is for polled I/O. The following 
program continually polls or inputs data from port FF until a non-zero number 
appears. The program then reads in data from port FE. In this application, port 
FF is used as a data ready signal for port FE. 



LOOP 



LD 


c, 


0FFH 


; C points at port FF 


IN 


B, 


(C) 


; input port FF to register B 


JR 


z, 


LOOP 


; continue polling until not zero 


IN 


A 


(0FEH) 


; input port FE to register A 



Nl 

Operation: (HL)<l(C), B<lB-1, HL<lHL + 1 

Format: 

Mnemonic: INI Operands: 



INput & Increment 



Object Code: 










I I I 

1 1 1 

i i i 


1 


1 





1 




1 1 l 
10 10 

1 1 1 








1 






ED 



A2 



Description: 

Register C contains the number of the input port. Data input is placed in 
memory at the address pointed at by HL. The contents of register C are placed 
on the bottom half (A0 through A7) of the address bus to select the I/O device at 
one of 256 possible ports. Register B may be used as a byte counter, and its 
contents are placed on the top half (A8 through A 15) of the address bus at this 
time. Then one byte from the selected port is placed on the data bus and written 
to the CPU. The contents of the HL register pair are then placed on the address 
bus and the input byte is written into the corresponding location of memory. 
Finally the byte counter is decremented and register pair HL is incremented. 

M cycles: 4 T states: 16(4,5,3,4) 4 MHzE.T.: 4.00 



213 



SERIES S EDITOR/ASSEMBLER 



Condition Bits Affected: 



S: 


Unknown 


Z: 


Set if B - 1 = 0; reset otherwise 


H: 


Unknown 


P/Vi 


Unknown 


N: 


Set 


C: 


Not affected 



Example: 

If the contents of register C are 07H, the contents of register B are 10H, the 
contents of the HL register pair are 1000H, and the byte 7BH is available at the 
peripheral device mapped to I/O port address 07H, then after the execution of 

INI 

memory location 1000H will contain 7BH, the HL register pair will contain 
1001H, and register B will contain 0FH. 



The following program will input data from input ports 1 through 80 and place 
the data into a buffer in memory. 



LOOP 



LD 


B,80 


LD 


C,0 


LD 


HL, BUFF 


INC 


C 


INI 




JP 


NZ, LOOP 



INput Increment & Repeat 



Operation: (HL) <l(C), B<lB - 1, HL<]HL + 1 

Format: 

Mnemonic: INIR Operands: 



Object Code: 



1 


1 


1 





1 


1 





1 




1 





1 


1 








1 






ED 



B2 



214 



INPUT AND OUTPUT GROUP 



Description: 

Register C contains the number of the input port. The data input is placed in 
memory at the address pointed at by the HL register pair. The contents of 
register C are placed on the bottom half (A0 through A7) of the address bus to 
select the I/O device at one of 256 possible ports. Register B is used as a byte 
counter, and its contents are placed on the top half (A8 through A 15) of the 
address bus at this time. Then one byte from the selected port is placed on 
the data bus and written to the CPU. The contents of the HL register pair are 
placed on the address bus and the input byte is written into the corresponding 
location of memory. Then register pair HL is incremented, the byte counter is 
decremented. If decrementing causes B to go to zero, the instruction is 
terminated. If B is not zero, the PC is decremented by two and the instruction 
repeated. Note that if B is set to zero prior to instruction execution, 256 bytes 
of data will be input. Also interrupts will be recognized after each data transfer. 

If B¥=0: 

M cycles: 5 T states: 21(4,5,3,4,5) 4MHzE.T.: 5.25 

If B = 0: 

M cycles: 4 T states: 16(4,5,3,4) 4 MHz E.T.: 4.00 

Condition Bits Affected: 

S: Unknown 

Z: Set 

H: Unknown 

P/V: Unknown 

N: Set 

C: Not affected 

Example: 

If the contents of register C are 07H, the contents of register B are 03H, the 
contents of the HL register pair are 1000H, and the following sequence of 
bytes are available at the peripheral device mapped to I/O port of address 07H: 

51H 

A9H 

03H 

then after the execution of 

INIR 

the HL register pair will contain 1003H, register B will contain zero, and 

memory locations will have contents as follows: 



Locatior 


i Contents 


1000H 


51H 


100 1H 


A9H 


1002H 


03H 



215 



SERIES I EDITOR/ASSEMBLER 



Here is a program to input 80 bytes from I/O port number FF and put them into 
an 80-byte buffer starting at address BUFF. 

LD HL, BUFF ; HL points at first byte of buffer 

LD B, 80 ; load byte counter 

LD C, OFFH ; port FF 

IN IR ; input 80 bytes 

Note: this assumes that the input port can be synchronized with the input 
instructions. 



ND INput & Decrement 

Operation: (HL)<l(C), B<lB -1, HL<) HL~ 1 

Format: 

Mnemonic: IND Operands: 

Object Code: 

I I I I | 

ED 

AA 



Description: 

The contents of register C are placed on the bottom half (A0 through A7) of the 
address bus to select the I/O device at one of 256 possible ports. Register B may 
be used as a byte counter, and its contents are placed on the top half (A8 
through A 15) of the address bus at this time. Then one byte from the selected 
port is placed on the data bus and written to the CPU. The contents of the HL 
register pair are placed on the address bus and the input byte is written into the 
corresponding location of memory. Finally the byte counter and register pair HL 
are decremented. 

M cycles: 4 T states: 16(4,5,3,4) 4 MHz EX: 4.00 

Condition Bits Affected: 

S: Unknown 

Z: .Set if B - 1 = 0; reset otherwise 

H: Unknown 

P/V: Unknown 

N: Set 

C: Not affected 



1 


1 


1 





1 


1 





1 




1 





1 





1 





1 






216 



1 PUTAN D OUTPUT GROUI 

mmmMM 



Example: 

If the contents of register C are 07H, the contents of register B are 10H, the 
contents of the HL register pair are 1000H, and the byte 7BH is available at the 
peripheral device mapped to I/O port address 07H, then after the execution of 

IND 

memory location 1000H will contain 7BH, the HL register pair will contain 

0FFFH, and register B will contain 0FH. 



INDR INput Decrement & Repeat 

Operation: (HL) <l (C), B <l B - 1 , HL<lHL - 1 

Format: 

Mnemonic: INDR Operands: 



Object Code: 



1 


1 


1 





1 


1 





1 




1 





1 


1 


1 





1 






ED 



BA 



Description: 

The contents of register C are placed on the bottom half (A0 through A7) of the 
address bus to select the I/O device at one of 256 possible ports. Register B is 
used as a byte counter, and its contents are placed on the top half (A8 through 
A 15) of the address bus at this time. Then one byte from the selected port 
is placed on the data bus and written to the CPU. The contents of the HL 
register pair are placed on the address bus and the input byte is written into 
the corresponding location of memory. Then HL and the byte counter 
are decremented. If decrementing causes B to go to zero, the instruction is 
terminated. If B is not zero, the PC is decremented by two and the instruction 
repeated. Note that if B is set to zero prior to instruction execution, 256 bytes of 
data will be input. Also interrupts will be recognized after each data transfer. 

If B¥=0: 

M cycles: 5 T states: 21(4,5,3,4,5) 4 MHz E.T.: 5.25 

IfB=0: 

M cycles: 4 T states: 16(4,5,3,4) 4 MHz E.T.: 4.00 



217 



SERIES S EDITOR/ASSEMBLER 



Condition Bits Affected: 



S: 


Unknown 


Z: 


Set 


H: 


Unknown 


P/V: 


Unknown 


N: 


Set 


C: 


Not affected 



Example: 

If the contents of register C are 07H, the contents of register B are 03H, the 
contents of the HL register pair are 1000H, and the following sequence of bytes 
are available at the peripheral device mapped to I/O port address 07H: 

51H 
A9H 
03 H 

then after the execution of 

INDR 

the HL register pair will contain 0FFDH, register B will contain zero, and 
memory locations will have contents as follows: 

Location Contents 

0FFEH 03 H 

0FFFH A9H 

1000H 51H 



OUT (n),A 



OUTput 



Operation: (n)<0A 

Format: 

Mnemonic: OUT Operands: (n), A 



Object Code: 



1 


1 





1 








1 


1 




n 


n 


n 


n 


n 


n 


n 


n 



D3 



218 



INPUT AND OUTPUT GROUP 



Description: 

The operand n is placed on the bottom half (A0 through A7) of the address 
bus to select the I/O device at one of 256 possible ports. The contents of the 
Accumulator (register A) also appear on the top half (A8 through A 15) of the 
address bus at this time. Then the byte contained in the Accumulator is placed 
on the data bus and written into the selected peripheral device. 

M cycles: 3 T states: 11(4,3,4) 4 MHz E.T.: 2.75 
Condition Bits Affected: None 

Example: 

If the contents of the Accumulator are 23H, then after the execution of 
OUT 01H,A 

the byte 23H will have been written to the peripheral device mapped to I/O port 
address 01H. 

OUT (C),r ouiput 

Operation: (C) <) X 

Format: 

Mnemonic: OUT Operands: (C), r 



ED 



Object Code: 










1110 

i i i 


1 


1 





1 




1 1 1 

1 r r 

i i i 


r 








1 



Description: 

The contents of register C are placed on the bottom half (A0 through A7) of the 
address bus to select the I/O device at one of 256 possible ports. The contents of 
Register B are placed on the top half (A8 through A 15) of the address bus at this 
time. Then the byte contained in register r is placed on the data bus and written 
into the selected peripheral device. Register r identifies any of the CPU registers 
shown in the following table, which also shows the corresponding three-bit "r" 
field for each which appears in the assembled object code: 



219 



SERIES I EDITOR/ASSEMBLER 



gister 


r 


B 


000 


C 


001 


D 


010 


E 


011 


H 


100 


L 


101 


A 


111 



M cycles: 3 T states: 12(4,4,4) 4 MHz E.T.: 3.00 
Condition Bits Affected: None 

Example: 

If the contents of register C are 01H and the contents of register D are 5AH, 
after the execution of 

OUT (C),D 

the byte 5AH will have been written to the peripheral device mapped to I/O port 
address 01H. 



U 1 I OUTput & Increment 

Operation: (C)0(HL),B<lB-1,HL<]HL + 1 



Format: 

Mnemonic: OUTI Operands: 

Object Code: 



1 


1 


1 


1 



1 


1 


1 





1 




1 





1 











1 


1 



ED 



A3 



Description: 

The contents of the HL register pair are placed on the address bus to select a 
location in memory. The byte contained in this memory location is temporarily 
stored in the CPU. Then, after the byte counter (B) is decremented, the contents 
of register C are placed on the bottom half (A0 through A7) of the address bus 
to select the I/O device at one of 256 possible ports. Register B may be used as 
a byte counter, and its decremented value is placed on the top half (A8 through 



220 



INPUT AND OUTPUT GROUP 



A 15) of the address bus. The byte to be output is placed on the data bus and 
written into selected peripheral device. Finally the register pair HL is 
incremented. 

M cycles: 4 T states: 16(4,5,3,4) 4 MHz E.T.: 4.00 



Condition Bits Affected: 



S 

z 

H 

P/V: 

N: 

C: 



Unknown 

Set if B - 1 = 

Unknown 

Unknown 

Set 

Not affected 



0; reset otherwise 



Example: 

If the contents of register C are 07H, the contents of register B are 10H, the 
contents of the HL register pair are 1000H, and the contents of memory address 
1000H are 59H, then after the execution of 

OUTI 

register B will contain 0FH, the HL register pair will contain 100 1H, and the 
byte 59H will have been written to the peripheral device mapped to I/O port 
address 07H. 



Oti n 
I 1 H OuTput Increment & Repeat 

Operation: (C)0(HL),B<lB"1,HL<lHL+1 



Format: 

Mnemonic: OTIR Operands: 

Object Code: 



1 


1 


1 





1 


1 





1 




1 





1 


1 








1 


1 



ED 



B3 



Description: 

The contents of the HL register pair are placed on the address bus to select a 
location in memory. The byte contained in this memory location is temporarily 
stored in the CPU. Then, after the byte counter (B) is decremented, the contents 
of register C are placed on the bottom half (A0 through A7) of the address bus 



221 



SERIES I EDITOR/ASSEMBLER 



to select the I/O device at one of 256 possible ports. Register B may be used as 
a byte counter, and its decremented value is placed on the top half (A8 through 
A 15) of the address bus at this time. Next the byte to be output is placed on the 
data bus and written into the selected peripheral device. Then register pair HL 
is incremented. If the decremented B register is not zero, the Program Counter 
(PC) is decremented by two and the instruction is repeated. If B has gone to 
zero, the instruction is terminated. Note that if B is set to zero prior to 
instruction execution, the instruction will output 256 bytes of data. Also, 
interrupts will be recognized after each data transfer. 

If B¥=0: 

M cycles: 5 T states: 21(4,5,3,4,5) 4 MHz E.T.: 5.25 

IfB = 0: 

M cycles: 4 T states: 16(4,5,3,4) 4 MHz E.T.: 4.00 

Condition Bits Affected: 



S: 


Unknown 


Z: 


Set 


H: 


Unknown 


P/V: 


Unknown 


N: 


Set 


C: 


Not affected 



Example: 

If the contents of register C are 07H, the contents of register B are 03H, the 
contents of the HL register pair are 1000H, and memory locations have the 
following contents: 

Location Contents 



1000H 


51H 


1001H 


A9H 


1002H 


03H 


then after the execution of 


OTIR 





the HL register pair will contain 1003H, register B will contain zero, and a 
group of bytes will have been written to the peripheral device mapped to I/O 
port address 07H in the following sequence: 

51H 

A9H 

03H 



222 



INPUT AND OUTPUT GROUP 



OUTD OUTput & Decrement 

Operation: (C)<](HL), BOB- 1,HL<lHL-1 



Format: 

Mnemonic: OUTD Operands: 



Object Code: 










I I I 

1110 

i i i 


1 


1 





1 




1 1 l 

10 10 

1 1 1 


1 





1 


1 



ED 



AB 



Description: 

The contents of the HL register pair are placed on the address bus to select a 
location in memory. The byte contained in this memory location is temporarily 
stored in the CPU. Then, after the byte counter (B) is decremented, the contents 
of register C are placed on the bottom half (A0 through A7) of the address bus 
to select the I/O device at one of 256 possible ports. Register B may be used as 
a byte counter, and its decremented value is placed on the top half (A8 through 
A 15) of the address bus at this time. Next the byte to be output is placed on the 
data bus and written into the selected peripheral device. Finally the register pair 
HL is incremented. 

M cycles: 4 T states: 16(4,5,3,4) 4 MHz E.T.: 4.00 

Condition Bits Affected: 

S: Unknown 

Z: Set if B — 1 — 0; reset otherwise 

H: Unknown 

P/V: Unknown 

N: Set 

C: Not affected 

Example: 

If the contents of register C are 07H, the contents of register B are 10H, the 

contents of the HL register pair are 1000H, and the contents of memory location 

1000H are 59H, after the execution of 

OUTD 

register B will contain 0FH, the HL register pair will contain 0FFFH, and the 

byte 59H will have been written to the peripheral device mapped to I/O port 

address 07H. 



223 



SERIES 1 EDITOR/ASSEMBLER 



Object Code: 




i i i i I 

1110 11 

i i i i i 


1 

1 

I 




1 1 1 1 1 

10 1110 

1 1 1 1 1 


1 
1 1 

1 



OTD R OUTput Decrement & Repeat 

Operation: (C) <1 (HL), B <] B - 1 , HL<l HL - 1 

Format: 

Mnemonic: OTDR Operands: 



ED 



BB 



Description: 

The contents of the HL register pair are placed on the address bus to select a 
location in memory. The byte contained in this memory location is temporarily 
stored in the CPU. Then, after the byte counter (B) is decremented, the contents 
of register C are placed on the bottom half (A0 through A7) of the address bus 
to select the I/O device at one of 256 possible ports. Register B may be used as 
a byte counter, and its decremented value is placed on the top half (A8 through 
A 15) of the address bus at this time. Next the byte to be output is placed on the 
data bus and written into the selected peripheral device. Then register pair HL is 
decremented and if the decremented B register is not zero, the Program Counter 
(PC) is decremented by 2 and the instruction is repeated. If B has gone to zero, 
the instruction is terminated. Note that if B is set to zero prior to instruction 
execution, the instruction will output 256 byte of data. Also, interrupts will be 
recognized after each data transfer. 

If B*0: 

M cycles: 5 T states: 21(4,5,3,4,5) 4 MHz E.T.: 5.25 

If B = 0: 

M cycles: 4 T states: 16(4,5,3,4) 4 MHz E.T.: 4.00 

Condition Bits Affected: 

S: Unknown 

Z: Set 

H: Unknown 

P/V: Unknown 

N: Set 

C: Not affected 



JtMWillMl iliilliW C^iiM^^ 



224 



INPUT AND OUTPUT GROUP 



Example: 

If the contents of register C are 07H, the contents of register B are 03H, the 
contents of the HL register pair are 1000H, and memory locations have the 
following contents: 

Location Contents 

0FFEH 51H 

0FFFH A9H 

1000H 03H 

then after the execution of 

OTDR 

the HL register pair will contain 0FFDH, register B will contain zero, and a 

group of bytes will have been written to the peripheral device mapped to I/O 

port address 07H in the following sequence: 

03H 
A9H 
51H 



225 



APPENDIX 



Appendix A /Using the TPSRC Utility 
(Disk Systems Only) 

This utility allows disk systems to: 

A. Read the source tapes created by the tape version of the Editor/ Assembler, 
and copy these to disk. 

B. Copy a disk object file (machine-language program) onto tape in the 
"system" format. 

Under trsdos ready, type tpsrc (ENTER) . The program will start and ask you to 
select either (1) source tape input or (2) object tape output. 

Source Tape Input 

If you type 1 CENTER) , the program will tell you to get the recorder ready. Get 
your recorder ready to play the source tape (created by the w command of the 
Tape Editor/ Assembler). Then press (ENTER) . 

tpsrc will read the tape and create a disk file with the same name as the tape 
and with the extension /src. The resultant file may be loaded by the Disk Editor/ 
Assembler (l command). 

Object Tape Output 

If you type 2 (ENTER) , the program will ask you for the name of the disk file. 
(The file must be in the correct program format, as created by the Disk Editor/ 
Assembler a command.) Type in the file name and press (ENTER) . 

Next, tpsrc will prompt you to get the recorder ready. Using a blank tape, 
prepare the recorder to record. Then press (ENTER) , tpsrc will then write out the 
object tape. The object tape will be given the name of the disk object file. 

The resultant tape is in the system format, and may be loaded according to the 
instructions in Section 5. 



227 



SERIES I EDITOR/ASSEMBLER 



MmssMimmmiBmK%x)amB^>BV&?3<m^mM<aisi>*»g}K 



Appendix B/ Model I Subroutines 

These are subroutines which are in the Read Only Memory (rom) of your Model 
I Level I or Level II basic Computer. You can call them using an assembly 
language program. 

The left-hand column lists the subroutines. The next columns demonstrate 
example assembly language programs which call these subroutines. 

If you have a Model I disk system, you can also call subroutines which are a 
part of your trs-80 Disk Operating System (trsdos). These are listed in your 
Model I "trsdos Disk basic Reference Manual." 

The Model HI basic subroutines are listed in the ' 'trs-80 Model III Operation 
and basic Language Reference Manual." (See the Appendix of the Operation 
Section.) The Model III trsdos subroutines are in the "Technical Information" 
of the "Model III Disk System's Owners Manual." 



Level I BASIC Subroutines 



KEYBOARD SCAN 
A-register contains input 
byte; input byte is displayed 
at current cursor. 



WAIT 



CALL 
JR 



0B40H 
Z.WAIT 



iSCAN 

iZ= 1 IF KB CLEAR 



DISPLAY BYTE 
AT CURSOR 



PUSH 


DE 


MUST SAVE 


PUSH 


IY 


DE &: IY 


LD 


A.20H 


BYTE TO DISPLA 


RST 


10H 


DISPLAY BYTE 


POP 


IY 


RESTORE 


POP 


DE 


DE & IY 



TURN ON 

CASSETTE 

On board cassette is 
turned on via remote plu£ 



CALL 



0FE3H 



iTURN ON CASSETTE 



SAVE MEMORY 
TO CASSETTE 

Cassette is 
turned off 



CALL 


0FE9H 


iTURN ON CASSETTE 


LD 


HL.700H 


iSTART ADDRESS 


LD 


DE*7100H 


iLAST+i ADDRESS 


CALL 


0F4BH 


iSAOE IT 



228 



LOAD MEMORY FROM 
CASSETTE 

On return 

HL = last + 1 address 

Z = Oif 

checksum error 

Z = 1 if 

checksum OK 

Cassette is 

turned off 



CALL 



0EF4H 



5 TURN ON & READ 



RETURN TO 
LEVEL I BASIC 



Press Reset 

JP 

JP 01C9H 



i POWER UP 

i RE-ENTRY WITH READY 



Level II BASIC Subroutines 



TURN ON CURSOR 
CHARACTER 



KEYBOARD SCAN 
A-register contains byte when 
loop falls through. 
Byte is not displayed on 
Screen! 



DISPLAY BYTE 
AT CURSOR 



AGN 



DEFINE DRIVE 



PUSH 


DE 


iMUST SAVE 


PUSH 


IY 


! DE & IY 


LD 


A.0EH 


5 0EH IS CURSOR BYTE 


CALL 


33H 


; DISPLAY ROUTINE 


POP 


IY 


5 RESTORE 


POP 


DE 


i DE & IY 


PUSH 


DE 


iMUST SAME 


PUSH 


IY 


i DE & IY 


CALL 


2BH 


iSCAN ROUTINE 


OR 


A 


!A=0 IF KB CLEAR 


JR 


Z.AGN 


5 BRANCH IF NO BYTE 


POP 


IY 


5 RESTORE 


POP 


DE 


! DE &: IY 


PUSH 


DE 


5MUST SAVE 


PUSH 


IY 


! DE & IY 


LD 


A.20H 


iBYTE TO DISPLAY 


CALL 


33H 


.DISPLAY 


POP 


IY 


i RESTORE 


POP 


DE 


5 DE & IY 



; A-REGISTER SPECIFIES CASSETTE (0 OR 1) 

LD A.0 

CALL 0212H 



5 ON BOARD CASSETTE 
! DEFINE DRIVE 



WRITE LEADER 
AND SYNC BYTE 



CALL 



I287H 



TURN OFF CASSETTE 



CALL 



I1F8H 



229 



SERIES I EDITOR/ASSEMBLER 



SAVE MEMORY 

TO CASSETTE 

User must CALL 264H often 
enough to keep up with 500 
baud. Timing is automatic. 



LOOK FOR LEADER 
AND SYNC BYTE 

LOAD MEMORY FROM 

CASSETTE 

Your program must CALL 
0235H often enough to keep 
up with 500 baud, and must 
do its own checksum if 
desired. A-register contains 
byte read. The user must turn 
off the cassette (CALL 
01F8H) when all bytes have 
been read. 

RETURN TO 
LEVEL II BASIC 

OUTPUT TO LINE PRINTER 
(LEVEL II ONLY) 



PRTOUT 



PRTLP8 



LD 


A»0 


5 0N BOARD CASSETTE 


CALL 


0212H 


i DEFINE DRIVE 


CALL 


0287H 


! WRITE LEADER 


LD 


A,20H 


iBYTE TO RECORD 


CALL 


02G4H 


5 OUTPUT BYTE 


CALL 


01F8H 


5CASSETTE OFF 


CALL 


029BH 




LD 


A»0 


; DEFINE DRIVE 


CALL 


02J2H 


5 FIND SYNC BYTE 


CALL 


029GH 


5 READ ONE BYTE 


CALL 


0235H 





Press 

JP 

JP 



RESET 



iLIKE POWER UP 

1A19H iRE-ENTRY 

!PUT ASCII BYTE IN 
iA-REGISTER AND CALL 

PRTOUT 
5 BUSY CONDITION TESTED 

FOR 



E>!>! 




5 SAVE REGS, 


LD 


HL.37E8H 


5 LOAD LP POINTER 
IN HL 


LD 


Di(HL) 


5 LOAD LP STATUS BYTE 


BIT 


7»D 


:IS THE PRINTER 


JP 


NZ.PRTLPB 


BUSY? 


LD 


(HL) >A 




EXX 




i OUTPUT BYTE TO 


RET 




PRINTER 



230 



APPENDIX 



Appendix C/Z-80 Status Indicators (Flags) 

The flag register (f and f') supplies information to the user regarding the status 
of the z-80 at any given time. The bit positions for each flag are shown below: 

7 6 5 4 3 2 10 



S Z X H X P/V N C 



WHERE: 


C 


= CARRY FLAG 


N 


= ADD/SUBTRACT FLAG 


P/V 


= PARITY/OVERFLOW FLAG 


H 


= HALF-CARRY FLAG 


Z 


= ZERO FLAG 


S 


= SIGN FLAG 


X 


- NOT USED 



Each of the two z-80 Flag Registers contains 6 bits of status information which are 
set or reset by cpu operations. (Bits 3 and 5 are not used.) Four of these bits are 
testable (c,p/v,z and s) for use with conditional jump, call or return instructions. 
Two flags are not testable (h,n) and are used for bcd arithmetic. 

Carry Flag (C) 

The cany bit is set or reset depending on the operation begin performed. For 'add' 
instructions that generate a cany and 'subtract' instructions that generate no bor- 
row, the Cany Flag will be set. The Carry Flag is reset by an add that does not 
generate a cany and a 'subtract' that generates a bonow. This saved cany facil- 
itates software routines for extended precision arithmetic. Also, the 'daa' instruc- 
tion will set the Carry Flag if the conditions for making the decimal adjustment 
are met. 

For instructions rla, rra, rls and rrs, the cany bit is used as a link between the 
lsb and MSB for any register or memory location. During instructions rlca, rlcs 
and sla's, the cany contains the last value shifted out of bit 7 of any register or 
memory location. During instructions rrca, rrcs, sra's and srl's the cany con- 
tains the last value shifted out of bit of any register or memory location. 

For the logical instructions and's, or's and xor's, the cany will be reset. 

The Cany Flag can also be set (scf) and complemented (ccf). 

Add/Subtract Flag (N) 

This flag is used by the decimal adjust accumulator instruction (daa) to distingiush 
between 'add' and 'subtract, instructions. For all 'add' instructions, n will be 
set to a 'o.' For all 'subtract' instructions, n will be set to a "l." 



231 



SERIES 1 EDITOR/ASSEMBLER 



Parity/Overflow Flag (P/V) 

This flag is set to a particular state depending on the operation being performed. 

For arithmetic operations, this flag indicates an overflow condition when the result 
in the Accumulator is greater than the maximum possible number (+127) or is 
less than the minimum possible number ( - 128). This overflow condition can be 
determined by examining the sign bits of the operands. 

For addition, operands with different signs will never cause overflow. When add- 
ing operands with like signs and the result has a different sign, the overflow flag 
is set. For example: 

+ 120 = 0111 1000 ADDEND 

+ 105 = 0110 1001 AUGEND 

+ 225 1110 0001 (-95) SUM 

The two numbers added together has resulted in a number that exceeds + 127 and 
the two positive operands has resulted in a negative number ( - 95) which is incor- 
rect. The overflow flag is therefore set. 

For subtraction, overflow can occur for operands of unlike signs. Operands of like 
sign will never cause overflow. For example: 

+ 127 0111 1111 MINUEND 

(-)-64 1100 0000 SUBTRAHEND 

+ 191 1011 1111 DIFFERENCE 

The minuend sign has changed from a positive to a negative, giving an incorrect 
difference. Overflow is therefore set. 

Another method for predicting an overflow is to observe the carry into and out of 
the sign bit. If there is a carry in and no carry out, or if there is no carry in and a 
carry out, then overflow has occurred. 

This flag is also used with logical operations and rotate instructions to indicate the 
parity of the result. The number of f bits in a byte are counted. If the total is odd, 
'odd' parity (p = o) is flagged. If the total is even, 'even' parity is flagged (p= l). 

During search instructions (cpi,cpir,cpd,cpdr) and block transfer instructions 
(ldi,ldir,ldd,lddr) the p/v flag monitors the state of the byte count register (bc). 
When decrementing, the byte counter results in a zero value, the flag is reset to 0, 
otherwise the flag is a Logic 1 . 

During ld a,i and ld a,r instructions, the p/v flag will be set with the contents of 
the interrupt enable flip-flop (IFF2) for storage or testing. 

When inputting a byte from an i/o device, in i,(c), the flag will be adjusted to 
indicate the parity of the data. 

The Half Carry Flag (H) 

The Half Carry Flag (h) will be set or reset depending on the carry and borrow 
status between bits 3 and 4 of an 8-bit arithmetic operation. This flag is used by 



232 



APPENDIX 



the decimal adjust accumulator instruction (daa) to correct the result of a packed 
bcd add or subtract operation. The h flag will be set (1) or rest (o) according to the 
following table: 



H 


ADD 


SUBTRACT 


1 



There is a carry from 
Bit 3 to Bit 4 
There is no carry from 
Bit 3 to Bit 4 


There is no borrow from 
Bit 4 

There is a borrow from 
Bit 4 



The Zero Flag (Z) 

The Zero Flag (z) is set or reset if the result generated by the execution of 
certain instructions is a zero. 

For 8-bit arithmetic and logical operations, the z flag will be set to a ' l ' if the 
resulting byte in the Accumulator is zero. If the byte is not zero, the z flag is 
reset to 'o.' 

For compare (search) instructions, the z flag will be set to a ' i ' if a comparison 
is found between the value in the Accumulator and the memory location pointed 
to by the contents of the register pair HL. 

When testing a bit in a register or memory location, the z flag will contain the 
complemented state of the indicated bit (see Bit b,s). 

When inputting or outputting a byte between a memory location and an i/o 
device (ini;IND;OUTI and outd), if the result of b-i is zero, the z flag is set, 
otherwise it is reset. Also for byte inputs from i/o devices using in r,(c), the z 
Flag is set to indicate a zero byte input. 

The Sign Flag (S) 

The Sign Flag (s) stores the state of the most significant bit of the Accumulator 
(Bit 7). When the zso performs arithmetic operations on signed numbers, binary 
two's complement notation is used to represent and process numeric 
information. A positive number is identified by a V in bit 7. A negative number 
is identified by a ' l '. The binary equivalent of the magnitude of a positive 
number is stored in bits to 6 for a total range of from to 127. A negative 
number is represented by the two's complement of the equivalent positive 
number. The total range for negative numbers is from - 1 to - 128. 

When inputting a byte from a i/o device to a register, in r,(c) the s flag will 
indicate either positive (s = o) or negative (s= l) data. 



233 



SERIES S EDITOR/ASSEMBLER 



Appendix D 
Numeric List of Instruction Set 

Following is a listing of object codes in numerical order in column two followed by the nmemonic or source 
statement in column four. 



LOC 


OBJ CODE 


STMT 


SOURCE STATEMENT 


LOC 


OBJ CODE 


STMT 


SOURCE STATEMENT 


0000 


00 


1 


NOP 


004E 


35 


54 


DEC (HL) 


0001 


018405 


2 


LD BC.NN 


004F 


3620 


55 


LD (HL),N 


0004 


02 


3 


LD (BC),A 


0051 


37 


56 


SCF 


0005 


03 


4 


1NCBC 


0052 


382E 


57 


JR C.DIS 


0006 


04 


5 


1NCB 


0054 


39 


58 


ADD HL.SP 


0007 


05 


6 


DECB 


0055 


3A8405 


59 


LD A,(NN) 


0008 


0620 


7 


LD B,N 


0058 


3B 


60 


DEC SP 


000A 


07 


8 


RLCA 


0059 


3C 


61 


INC A 


000B 


08 


9 


EX AF.AF' 


005A 


3D 


62 


DEC A 


oooc 


09 


10 


ADD HL,BC 


005B 


3E20 


63 


LD A,N 


00OD 


0A 


11 


LD A,(BC) 


005D 


3F 


64 


CCF 


00OE 


0B 


12 


DEC BC 


005 E 


40 


65 


LD B,B 


000F 


OC 


13 


INCC 


005 F 


41 


66 


LD B,C 


0010 


OD 


14 


DECC 


0060 


42 


67 


LD B,D 


0011 


0E20 


15 


LD C,N 


0061 


43 


68 


LD B,E 


0013 


OF 


16 


RRCA 


0062 


44 


69 


LD B,H(NN) 


0014 


I02E 


17 


DJNZ DIS 


0063 


45 


70 


LD B,L 


0016 


118405 


18 


LD DE.NN 


0064 


46 


71 


LD B,(HL) 


0019 


12 


19 


LD (DE),A 


0065 


47 


72 


LDB,A 


001 A 


13 


20 


INC DE 


0066 


48 


73 


LD C.B 


001 B 


14 


21 


INCD 


0067 


49 


74 


LD C,C 


001C 


15 


22 


DECD 


0068 


4A 


75 


LD CD 


001D 


1620 


23 


LD D,N 


0069 


4B 


76 


LD C,E 


001F 


17 


24 


RLA 


006A 


4C 


77 


LD C,H 


0020 


182E 


25 


JR DIS 


006B 


4D 


78 


LD C.L 


0022 


19 


26 


ADD HL.DE 


006C 


4E 


79 


LD C,(HL) 


0023 


1A 


27 


LD A,(DE) 


006D 


4F 


80 


LDC.A 


0024 


IB 


28 


DEC DE 


006E 


50 


81 


LD D,B 


0025 


1C 


29 


1NCE 


006F 


51 


82 


LD D,C 


0026 


ID 


30 


DECE 


0070 


52 


83 


LDD,D 


0027 


1E20 


31 


LD E,N 


0071 


53 


84 


LD D,E 


0029 


IF 


32 


RRA 


0072 


54 


85 


LD D,H 


002A 


202E 


33 


JR NZ.DIS 


0073 


55 


86 


LD D,L 


002C 


218405 


34 


LD HL.NN 


0074 


56 


87 


LD D,(HL) 


002F 


228405 


35 


LD (NN),HL. 


0075 


57 


88 


LD D,A 


0032 


23 


36 


INC HL 


0076 


58 


89 


LD E,B 


0033 


24 


37 


INCH 


0077 


59 


90 


LD E,C 


0034 


25 


38 


DECH 


0078 


5A 


91 


LD E,D 


0035 


2620 


39 


LD H,N 


0079 


5B 


92 


LDE,E 


0037 


27 


40 


DAA 


007A 


5C 


93 


LD E,H 


0038 


282E 


41 


JR Z.DIS 


007B 


5D 


94 


LD E,L 


003A 


29 


42 


ADD HL.HL 


007C 


5E 


95 


LD E,(HL) 


003B 


2A8405 


43 


LD HL.(NN) 


007D 


5F 


96 


LD E,A 


003E 


2B 


44 


DECHL 


007E 


60 


97 


LD H,B 


003F 


2C 


45 


INCL 


007F 


61 


98 


LDH,C 


0040 


2D 


46 


DEC L. 


0080 


62 


99 


LD H,D 


0041 


2E20 


47 


LD L,N 


0081 


63 


100 


LD H,E 


0043 


2F 


48 


CPL 


0082 


64 


101 


LDH,H 


0044 


302E 


49 


JR NC.DIS 


0083 


65 


102 


LD H.L 


0046 


318405 


50 


LD SP.NN 


0084 


66 


103 


LD H,(HL) 


0049 


328405 


51 


LD (NN),A 


0085 


67 


104 


LD H,A 


004C 


33 


52 


INCSP 


0086 


68 


105 


LD L,B 


004D 


34 


53 


INC (HL) 


0087 


69 


106 


LD L,C 



234 



APPENDIX 



LOC 


OBJ CODE 


STMT 


SOURCE STATEMENT 


LOC 


OBJ C0D1 


E STMT 


SOURCE STATEMENT 


0088 


6A 


107 


LDL,D 


00C5 


A7 


168 


AND A 


0089 


6B 


108 


LD L,E 


00C6 


A8 


169 


XORB 


008A 


6C 


109 


LDL.H 


00C7 


A9 


170 


XORC 


008 B 


6D 


110 


LDL,L 


00C8 


AA 


171 


XORD 


008C 


6E 


111 


LD L,(HL) 


00C9 


AB 


172 


XORE 


008D 


6F 


112 


LDL.A 


OOCA 


AC 


173 


XORH 


008E 


70 


113 


LD (HL),B 


OOCB 


AD 


174 


XORL 


008F 


71 


114 


LD(HL),C 


OOCC 


AE 


175 


XOR (HL) 


0090 


72 


115 


LD(HL),D 


OOCD 


AF 


176 


XORA 


0091 


73 


116 


LD(HL),E 


OOCE 


BO 


177 


ORB 


0092 


74 


117 


LD(HL),H 


OOCF 


Bl 


178 


ORC 


0093 


75 


118 


LD(HL),L 


00D0 


B2 


179 


OR D 


0094 


76 


119 


HALT 


00D1 


B3 


180 


ORE 


0095 


77 


120 


LD(HL),A 


0002 


B4 


181 


ORH 


0096 


78 


121 


LD A,B 


00D3 


B5 


182 


ORL 


0097 


79 


122 


LD A,C 


00D4 


B6 


183 


OR (HL) 


0098 


7A 


123 


LD A,D 


00D5 


B7 


184 


OR A 


0099 


7B 


124 


LD A,E 


00D6 


B8 


185 


CPB 


009A 


7C 


125 


LD A,H 


00D7 


B9 


186 


CPC 


009B 


7D 


126 


LD A,L 


00D8 


BA 


187 


CPD 


009C 


7E 


127 


LD A,(HL) 


O0D9 


BB 


188 


CPE 


009D 


7F 


128 


LD A, A 


OODA 


BC 


189 


CPH 


009E 


80 


129 


ADDA,B 


OODB 


BD 


190 


CPL 


009F 


81 


130 


ADD A,C 


OODC 


BE 


191 


CP(HL) 


00A0 


82 


131 


ADD A,D 


OODD 


BF 


192 


CP A 


00A1 


83 


132 


ADDA.E 


OODE 


CO 


193 


RET NZ 


00A2 


84 


133 


ADD A,H 


OODF 


CI 


194 


POPBC 


00A3 


85 


134 


ADD A,L 


00E0 


C28405 


195 


JP NZ, NN 


00A4 


86 


135 


ADDA.(HL) 


00E3 


C38405 


196 


IPNN 


00A5 


87 


136 


ADD A, A 


00E6 


C48405 


197 


CALL NZ.NN 


00A6 


88 


137 


ADC A,B 


00E9 


C5 


198 


PUSH BC 


00A7 


89 


138 


ADC A,C 


OOEA 


C620 


199 


ADD A,N 


00A8 


8A 


139 


ADC A,D 


OOEC 


C7 


200 


RSTO 


00A9 


8B 


140 


ADC A,E 


OOED 


C8 


201 


RET Z 


OOAA 


8C 


141 


ADCA.H 


OOEE 


C9 


202 


RET 


OOAB 


8D 


142 


ADC A,L 


OOEF 


CA8405 


203 


JPZ.NN 


OOAC 


8E 


143 


ADCA.(HL) 


00F2 


CC8405 


204 


CALLZ.NN 


OOAD 


8F 


144 


ADCA.A 


00F5 


CD8405 


205 


CALL NN 


OOAE 


90 


145 


SUBB 


00F8 


CE20 


206 


ADC A,N 


OOAF 


91 


146 


SUBC 


OOFA 


CF 


207 


RST 8 


OOBO 


92 


147 


SUBD 


OOFB 


DO 


208 


RET NC 


00B1 


93 


148 


SUBE 


OOFC 


Dl 


209 


POPDE 


00B2 


94 


149 


SUBH 


OOFD 


D28405 


210 


IP NC,NN 


00B3 


95 


150 


SUBL 


0100 


D320 


211 


OUT ,NA 


00B4 


96 


151 


SUB (HL) 


0102 


D48405 


212 


CALL NC.NN 


00B5 


97 


152 


SUB A 


0105 


D5 


213 


PUSH DE 


00B6 


98 


153 


SBCA.B 


0106 


D620 


214 


SUB N 


00B7 


99 


154 


SBCA.C 


0108 


D7 


215 


RST 10H 


00B8 


9A 


155 


SBCA.D 


0109 


D8 


216 


RETC 


00B9 


9B 


156 


SBC A,E 


010A 


D9 


217 


EXX 


OOBA 


9C 


157 


SBC A,H 


010B 


DA8405 


218 


JPC.NN 


OOBB 


9D 


158 


SBCA.L 


010E 


DB20 


219 


IN A,N 


OOBC 


9E 


159 


SBC A,(HL) 


0110 


DC8405 


220 


CALL C.NN 


OOBD 


9F 


160 


SBC A,A 


0113 


DE20 


221 


SBCA.N 


OOBE 


AO 


161 


ANDB 


0115 


DF 


222 


RST 18H 


OOBF 


Al 


162 


ANDC 


0116 


EO 


223 


RET PO 


OOCO 


A2 


163 


ANDD 


0117 


El 


224 


POPHL 


00C1 


A3 


164 


ANDE 


0118 


E28405 


225 


JP PO,NN 


00C2 


A4 


165 


ANDH 


01 IB 


E3 


226 


EX (SP),HL 


00C3 


A5 


166 


ANDL 


one 


E48405 


227 


CALL PO,NN 


00C4 


A6 


167 


AND (HL) 


01 IF 


E5 


228 


PUSH HL 



235 



SERIES I EDITOR/ASSEMBLER 



1 


'^^^^MSfSM^^^^^^^^^S^^^X^^^k 


&:swt4MMitEm3^:'^sm.j%i^3tSi*i>'*abi£dmetBmsa 




LOC 


OBJ CODE 


STMT 


SOURCE STATEMENT 


LOC 


OBJ CODE 


STMT 


SOURCE STATEMENT 


0120 


E620 


229 


ANDN 


0192 


CB25 


290 


SLA L 


0122 


E7 


230 


RST 20H 


0194 


CB26 


291 


SLA (HL) 


0123 


E8 


231 


RET PE 


0196 


CB27 


292 


SLA A 


0124 


E9 


232 


JP (HL) 


0198 


CB28 


293 


SRAB 


0125 


EA8405 


233 


JP PE,NN 


019A 


CB29 


294 


SRAC 


0128 


EB 


234 


EX DE.HL 


0I9C 


CB2A 


295 


SRAD 


0129 


EC8405 


235 


CALL PE.NN 


019E 


CB2B 


296 


SRAE 


012C 


EE20 


236 


XORN 


01A0 


CB2C 


297 


SRAH 


012E 


EF 


237 


RST 28H 


01A2 


CB2D 


298 


SRAL 


012F 


F0 


238 


RETP 


01A4 


CB2E 


299 


SRA (HL) 


0130 


Fl 


239 


POP AF 


0IA6 


CB2F 


300 


SRAA 


0131 


F28405 


240 


JPP.NN 


01A8 


CB38 


301 


SRLB 


0134 


F3 


241 


DI 


01AA 


CB39 


302 


SRLC 


0135 


F48405 


242 


CALL P,NN 


01AC 


CB3A 


303 


SRLD 


0138 


F5 


243 


PUSH AF 


01AE 


CB3B 


304 


SRL E 


0139 


F620 


244 


ORN 


01B0 


CB3C 


305 


SRLH 


013B 


F7 


245 


RST 30H 


01B2 


CB3D 


306 


SRL L 


013C 


F8 


246 


RETM 


01B4 


CB3E 


307 


SRL (HL) 


01 3D 


F9 


247 


L.D SP.HL 


01B6 


CB3F 


308 


SRL A 


013E 


FA8405 


248 


.IP M.NN 


01B8 


CB40 


309 


BITO.B 


0141 


FB 


249 


EI 


OIBA 


CB41 


310 


BITO.C 


0142 


FC8405 


250 


CALLM.NN 


01BC 


CB42 


311 


BITO.D 


0145 


FE20 


251 


CPN 


OIBE 


CB43 


312 


BITO.E 


0147 


FF 


252 


RST 38H 


OICO 


CB44 


313 


BITO.H 


0148 


CB00 


253 


RLCB 


01C2 


CB45 


314 


BITO.L 


014A 


CB01 


254 


RLCC 


01C4 


CB46 


315 


BIT O.(HL) 


014C 


CB02 


255 


RLCD 


01C6 


CB47 


316 


BITO.A 


014E 


CB03 


256 


RLC E 


01C8 


CB48 


317 


BIT I,B 


0150 


CB04 


257 


RLCH 


01CA 


CB49 


318 


BIT 1 ,C 


0152 


CB05 


258 


RLC L 


01CC 


CB4A 


319 


BIT I,D 


0154 


CB06 


259 


RLC (HL) 


01CE 


CB4B 


320 


BIT 1,E 


0156 


CB07 


260 


RLC A 


01D0 


CB4C 


321 


BIT l.H 


0158 


CB08 


261 


RRCB 


01D2 


CB4D 


322 


BIT 1,L 


015A 


CB09 


262 


RRCC 


01D4 


CB4E 


323 


BITl.(HL) 


015C 


CBOA 


263 


RRCD 


0ID6 


CB4F 


324 


BIT 1,A 


015E 


CBOB 


264 


RRCE 


01D8 


CB50 


325 


BIT 2,B 


0160 


CBOC 


265 


RRCH 


01DA 


CB51 


326 


BIT 2,C 


0162 


CBOD 


266 


RRCL 


01DC 


CB52 


327 


BIT2.D 


0164 


CBOE 


267 


RRC (HL) 


01 DE 


CB53 


328 


BIT 2,E 


0166 


CBOF 


268 


RRC A 


01E0 


CB54 


329 


BIT2.H 


0168 


CB10 


269 


RLB 


01E2 


CB55 


330 


BIT2X 


016A 


CBU 


270 


RLC 


01E4 


CB56 


331 


BIT2,(HL) 


016C 


CB12 


271 


RLD 


01E6 


CB57 


332 


BIT2.A 


016E 


CB13 


272 


RLE 


01E8 


CB58 


333 


BIT3.B 


0170 


CB14 


273 


RLH 


01EA 


CB59 


334 


BIT3.C 


0172 


CB15 


274 


RLL 


01 EC 


CB5A 


335 


BIT 3,D 


0174 


CB16 


275 


RL. (HL) 


01EE 


CB5B 


336 


BIT 3,E 


0176 


CB17 


276 


RLA 


01F0 


CB5C 


337 


BIT 3,H 


0178 


CB18 


277 


RR B 


01F2 


CB5D 


338 


BIT 3,L 


017A 


CB19 


278 


RRC 


01F4 


CB5E 


339 


BIT 3,(HL) 


017C 


CB1A 


279 


RRD 


01F6 


CB5F 


340 


BIT 3,A 


017E 


CB1B 


280 


RRE 


01F8 


CB60 


341 


BIT4.B 


0180 


CB1C 


281 


RRH 


01 FA 


CB61 


342 


BIT4.C 


0182 


CB1D 


282 


RRL 


01FC 


CB62 


343 


BIT4.D 


0184 


CB1E 


283 


RR (HL) 


01FE 


CB63 


344 


BIT4.E 


0186 


CB1F 


284 


RR A 


0200 


CB64 


345 


BIT4.H 


0188 


CB20 


285 


SLA B 


0202 


CB65 


346 


BIT4.L 


018A 


CB21 


286 


SLAC 


0204 


CB66 


347 


BIT4,(HL) 


018C 


CB22 


287 


SLAD 


0206 


CB67 


348 


BIT4.A 


018E 


CB23 


288 


SLAE 


0208 


CB68 


349 


BIT5.B 


0190 


CB24 


289 


SLA H 


020A 


CB69 


350 


BIT5.C 



236 



APPENDIX 



^■^^^ ■^■^^^^^^^^^^^^M^— ^^— ^^^^^^^^^^^^M^^^^^^^^^^^^^^H^^M^^^^^^^^^^^^^^^^M 



LOC 


OBJ CODE 


STMT 


SOURCE STATEMENT 


LOC 


OBJ CODE 


STMT 


SOURCE STATEMENT 


020C 


CB6A 


351 


BIT 5,D 


0286 


CBA7 


412 


RES 4, A 


020E 


CB6B 


352 


BIT 5,E 


0288 


CBA8 


413 


RES 5,B 


0210 


CB6C 


353 


BIT5.H 


028A 


CBA9 


414 


RES 5,C 


0212 


CB6D 


354 


BIT5.L 


028C 


CBAA 


415 


RES 5,D 


0214 


CB6E 


355 


BIT 5,(HL) 


028E 


CBAB 


416 


RES5.E 


0216 


CB6F 


356 


BIT5.A 


0290 


CBAC 


417 


RES 5,H 


0218 


CB70 


357 


BIT 6,B 


0292 


CBAD 


418 


RES5.L 


021A 


CB71 


358 


BIT 6,C 


0294 


CBAE 


419 


RES 5,(HL) 


021C 


CB72 


359 


BIT6.D 


0296 


CBAF 


420 


RES 5, A 


021E 


CB73 


360 


BIT6.E 


0298 


CBB0 


421 


RES 6,B 


0220 


CB74 


361 


BIT6.H 


029A 


CBB1 


422 


RES 6,C 


0222 


CB75 


362 


BIT6.L 


029C 


CBB2 


423 


RES 6,D 


0224 


CB76 


363 


BIT6,(HL) 


029E 


CBB3 


424 


RES 6,E 


0226 


CB77 


364 


BIT 6, A 


02A0 


CBB4 


425 


RES 6,H 


0228 


CB78 


365 


BIT7.B 


02A2 


CBB5 


426 


RES 6,L 


022A 


CB79 


366 


BIT7.C 


02A4 


CBB6 


427 


RES 6,(HL) 


022C 


CB7A 


367 


BIT7.D 


02A6 


CBB7 


428 


RES 6,A 


022E 


CB7B 


368 


BIT7.E 


02A8 


CBB8 


429 


RES 7,B 


0230 


CB7C 


369 


BIT7.H 


02AA 


CBB9 


430 


RES 7,C 


0232 


CB7D 


370 


BIT 7,L 


02AC 


CBBA 


431 


RES 7,D 


0234 


CB7E 


371 


BIT 7,(HL) 


02AE 


CBBB 


432 


RES 7,E 


0236 


CB7F 


372 


BIT7.A 


0280 


CBBC 


433 


RES 7,H 


0238 


CB80 


373 


RES0.B 


0282 


CBBD 


434 


RES 7,L 


023A 


CB81 


374 


RES 0,C 


0284 


CBBE 


435 


RES 7,(HL) 


023C 


CB82 


375 


RES 0,D 


0286 


CBBF 


436 


RES 7, A 


023E 


CB83 


376 


RES 0,E 


0288 


CBC0 


437 


SETO.B 


0240 


CB84 


377 


RES 0,H 


02BA 


CBC1 


438 


SET 0,C 


0242 


CB85 


378 


RES 0,L 


02BC 


CBC2 


439 


SET 0,D 


0244 


CB86 


379 


RES 0,(HL) 


02BE 


CBC3 


440 


SET 0,E 


0246 


CB87 


380 


RES 0,A 


02C0 


CBC4 


441 


SETO.H 


0248 


CB88 


381 


RES 1,B 


02C2 


CBC5 


442 


SET 0,L 


024A 


CB89 


382 


RES 1,C 


02C4 


CBC6 


443 


SETO.(HL) 


024C 


CB8A 


383 


RES 1,D 


02C6 


CBC7 


444 


SET 0,A 


024E 


CB8B 


384 


RES l,E 


02C8 


CBC8 


445 


SET 1,B 


0250 


CB8C 


385 


RES 1 ,H 


02CA 


CBC9 


446 


SET1.C 


0252 


CB8D 


386 


RES 1 ,L 


02CC 


CBCA 


447 


SET1,D 


0254 


CB8E 


387 


RES 1,(HL) 


02CE 


CBCB 


448 


SET 1,E 


0256 


CB8F 


388 


RES 1 ,A 


02D0 


CBCC 


449 


SET 1,H 


0258 


CB90 


389 


RES 2,B 


02D2 


CBCD 


450 


SET IT 


025A 


CB91 


390 


RES 2,C 


02D4 


CBCE 


451 


SET1,(HL) 


025C 


CB92 


391 


RES 2,D 


02D6 


CBCF 


452 


SET1.A 


025E 


CB93 


392 


RES 2,E 


02D8 


CBD0 


453 


SET 2,B 


0260 


CB94 


393 


RES 2,H 


02DA 


CBD1 


454 


SET 2,C 


0262 


CB95 


394 


RES 2,L 


02DC 


CBD2 


455 


SET 2,D 


0264 


CB96 


395 


RES 2,(HL) 


02DE 


CBD3 


456 


SET 2,E 


0266 


CB97 


396 


RES 2, A 


02E0 


CBD4 


457 


SET 2,H 


0268 


CB98 


397 


RES 3,B 


02E2 


CBD5 


458 


SET 2,L 


026A 


CB99 


398 


RES 3,C 


02E4 


CBD6 


459 


SET 2,(HL) 


026C 


CB9A 


399 


RES 3,D 


02E6 


CBD7 


460 


SET 2,A 


026E 


CB9B 


400 


RES 3,E 


02E8 


CBD8 


461 


SET 3,B 


0270 


CB9C 


401 


RES 3,H 


02EA 


CBD9 


462 


SET 3,C 


0272 


CB9D 


402 


RES 3,L 


02EC 


CBDA 


463 


SET 3,D 


0274 


CB9E 


403 


RES 3,(HL) 


02EE 


CBDB 


464 


SET 3,E 


0276 


CB9F 


404 


RES 3, A 


02F0 


CBDC 


465 


SET3.H 


0278 


CBAO 


405 


RES 4,B 


02F2 


CBDD 


466 


SET 3,L 


027A 


CBA1 


406 


RES 4,C 


02F4 


CBDE 


467 


SET 3,(HL) 


027C 


CBA2 


407 


RES 4,D 


02F6 


CBDF 


468 


SET 3,A 


027E 


CBA3 


408 


RES 4,E 


02F8 


CBEO 


469 


SET 4,B 


0280 


CBA4 


409 


RES 4,H 


02FA 


CBE1 


470 


SET 4,C 


0282 


CBA5 


410 


RES 4,L 


02FC 


CBE2 


471 


SET 4,D 


0284 


CBA6 


411 


RES 4,(HL) 


02FE 


CBE3 


472 


SET 4,E 



237 



SERGES 1 EDITOR/ASSEMBLER 



LOC 


OBJ CODE 


STIV 


0300 


CBE4 


473 


0302 


CBE5 


474 


0304 


CBE6 


475 


0306 


CBE7 


476 


0308 


CBE8 


477 


030A 


CBE9 


478 


0.30C 


CBEA 


479 


030E 


CBEB 


480 


0310 


CBEC 


481 


0312 


CBED 


482 


0314 


CBEE 


483 


0316 


CBEF 


484 


0318 


CBFO 


485 


031 A 


CBF1 


486 


03 1C 


CBF2 


487 


03 IE 


CBF3 


488 


0320 


CBF4 


489 


0322 


CBF5 


490 


0324 


CBF6 


491 


0326 


CBF7 


492 


0328 


CBF8 


493 


032A 


CBF9 


494 


032C 


CBFA 


495 


032E 


CBFB 


496 


0330 


CBFC 


497 


0332 


CBFD 


498 


0334 


CBFE 


499 


0336 


CBFF 


500 


0338 


DD09 


501 


033A 


DD19 


502 


033C 


DD2 18405 


503 


0340 


DD228405 


504 


0344 


DD23 


505 


0346 


DD29 


506 


0348 


DD2A8405 


507 


034C 


DD2B 


508 


034E 


DD3405 


509 


0351 


DD3505 


510 


0354 


DD360520 


511 


0358 


DD39 


512 


035A 


DD4605 


513 


035D 


DD4E05 


514 


0360 


DD5605 


515 


0363 


DD5E05 


516 


0366 


DD6605 


517 


0369 


DD6E05 


518 


036C 


DD7005 


519 


036F 


DD7105 


520 


0372 


DD7205 


521 


0375 


DD7305 


522 


0378 


DD7405 


523 


037B 


DD7505 


524 


037E 


DD7705 


525 


0381 


DD7E05 


526 


0384 


DD8605 


527 


0387 


DD8E05 


528 


038A 


DD9605 


529 


038D 


DD9E05 


530 


0390 


DDA605 


531 


0393 


DDAE05 


532 


0396 


DDB605 


533 



SOURCE STATEMENT 

SET 4,H 
SET4.L 
SET 4,(HL) 
SET 4, A 
SET5.B 
SET 5,C 
SET5,D 
SET5.E 
SET5,H 
SET 5.L 
SET 5,(HL) 
SET 5, A 
SET 6,B 
SET 6,C 
SET 6,D 
SET 6,E 
SET6.H 
SET 6,L 
SET 6,(HL) 
SET6.A 
SET 7,B 
SET 7,C 
SET 7,D 
SET 7,E 
SET 7.H 
SET 7,L 
SET 7,(HL) 
SET 7, A 
ADD IX, BC 
ADD IX, DE 
LD IX, NN 
LD (NN)JX 
INC IX 
ADD IX, IX 
LD IX,(NN) 
DEC IX 
INCUX + IND) 
DECUX + IND) 
LD(IX + IND),N 
ADD IX.SP 
LDB,{IX + IND) 
LDC.UX + IND) 
LDD,(IX + IND) 
LDE,(IX + IND) 
LDH,(IX + IND) 
LDL,(IX + IND) 
LD(IX + IND),B 



LD (IX + 
LD (IX + 
LD (IX + 
LD (IX + 
LD(IX + 
LD(IX + 
LD A,(IX 



IND),C 
IND),D 
IND),E 
IND),H 
IND),L 
IND),A 
+ IND) 



ADDA.(IX + IND) 
ADCA,(IX + IND) 
SUB(IX + IND) 
SBCA,(IX + IND) 
AND(IX + IND) 
XOR(IX + IND) 
OR(IX + IND) 



LOC 


OBJ CODE 


STMT 


0399 


DDBE05 


534 


039C 


DDE1 


535 


039E 


DDE3 


536 


03AO 


DDE5 


537 


03A2 


DDE9 


538 


03A4 


DDF9 


539 


03A6 


DDCB0506 


540 


03AA 


DDCB050E 


541 


03AE 


DDCB0516 


542 


03B2 


DDCB051E 


543 


03B6 


DDCB0526 


544 


03BA 


DDCB052E 


545 


03BE 


DDCB053E 


546 


03C2 


DDCB0546 


547 


03C6 


DDCB054E 


548 


03CA 


DDCB0556 


549 


03CE 


DDCB055E 


550 


03D2 


DDCB0566 


551 


03D6 


DDCB056E 


552 


03DA 


DDCB0576 


553 


03DE 


DDCB057E 


554 


03E2 


DDCB0586 


555 


03E6 


DDCB058E 


556 


03EA 


DDCB0596 


557 


03EE 


DDCB059E 


558 


03F2 


DDCB05A6 


559 


03F6 


DDCB05AE 


560 


03FA 


DDCB05B6 


561 


03FE 


DDCB05BE 


562 


0402 


DDCB05C6 


563 


0406 


DDCB05CE 


564 


040A 


DDCB05D6 


565 


040E 


DDCB05DE 


566 


0412 


DDCB05E6 


567 


0416 


DDCB05EE 


568 


041A 


DDCB05F6 


569 


041 E 


DDCB05FE 


570 


0422 


ED40 


571 


0424 


ED41 


572 


0426 


ED42 


573 


0428 


ED438405 


574 


042C 


ED44 


575 


042E 


ED45 


576 


0430 


ED46 


577 


0432 


ED47 


578 


0434 


ED48 


579 


0436 


ED49 


580 


0438 


ED4A 


581 


043A 


ED4B8405 


582 


043E 


ED4D 
ED4F 
ED5F 


583 


0440 


ED50 


584 


0442 


ED51 


585 


0444 


ED52 


586 


0446 


ED538405 


587 


044A 


ED56 


588 


044C 


ED57 


589 


044E 


ED58 


590 


0450 


ED59 


591 


0452 


ED5A 


592 


0454 


ED5B8405 


593 



SOURCE STATEMENT 

CP(IX + IND) 
POP IX 
EX (SP),IX 
PUSH IX 
IP (IX) 
LD SP.IX 
RLC(IX + IND) 
RRC(IX + IND) 
RL(IX + IND) 
RR(IX + IND) 
SLA(IX + IND) 
SRAOX + IND) 
SRL0X + IND) 
BIT0,(IX + IND) 
BIT 1,(IX + IND) 
BIT2,(IX + IND) 
BIT3,(IX + IND) 
BIT4,(IX + IND) 
BIT5,(IX + IND) 
BIT6,(IX + IND) 
BIT7,(IX + IND) 
RES0,(IX + IND) 
RES 1,(IX + IND) 
RES2,(IX + IND) 
RES3,(IX + IND) 
RES4,(IX + IND) 
RES5,(IX + IND) 
RES6,(IX + IND) 
RES7,(IX + IND) 
SET 0,(IX + IND) 
SET 1,(IX + IND) 
SET2,(IX + IND) 
SET3,(IX + IND) 
SET 4,(IX + IND) 
SET5.0X + IND) 
SET 6,(IX + IND) 
SET7,(IX + IND) 
INB,(C) 
OUT (C),B 
SBC HL.BC 
LD (NN),BC 
NEC 
RETN 
IM0 
LD I,A 
IN C,(C) 
OUT (C),C 
ADC HL,BC 
LD BC,(NN) 
RETI 
LD R,A 
LD A,R 
IND,(C) 
OUT (C),D 
SBC HL.DE 
LD (NN).DE 
IMI 
LD A,I 
IN E,(C) 
OUT (C),E 
ADC HL.DE 
LD DE,(NN) 



238 



APPENDIX 



LOC 


OBJ CODE 


STMT 


SOURCE STATEMENT 


LOC 


OBJ CODE 


STMT 


SOURCE STATEMENT 


045A 


ED60 


595 


IN H,(C) 


04DD 


FD7505 


648 


LD(IY + IND),L 


045C 


ED61 


596 


OUT (C),H 


04E0 


FD7705 


649 


LD(IY + IND),A 


045E 


ED62 


597 


SBCHL.HL 


04E3 


FD7E05 


650 


LDA,(IY + IND) 


0460 


ED67 


598 


RRD 


04E6 


FD8605 


651 


ADDA,(IY + IND) 


0462 


ED68 


599 


IN L.(C) 


04E9 


FD8E05 


652 


ADCA,(IY + IND) 


0464 


ED69 


600 


OUT(C),L 


04EC 


FD9605 


653 


SUB-{IY + IND) 


0466 


ED6A 


601 


ADC HL,HL 


04EF 


FD9E05 


654 


SBCA,(IY + IND) 


0468 


ED6F 


602 


RLD 


04F2 


FDA605 


655 


AND(IY + IND) 


046A 


ED72 


603 


SBC HL.SP 


04F5 


FDAE05 


656 


XOROY + IND) 


046C 


ED738405 


604 


LD(NN),SP 


04F8 


FDB605 


657 


OR(IY + IND) 


0470 


ED78 


605 


INA,(C) 


04FB 


FDBE05 


658 


CP(IY + IND) 


0472 


ED79 


606 


OUT(C),A 


04FE 


FDE1 


659 


POPIY 


0474 


ED7A 


607 


ADC HL.SP 


0500 


FDE3 


660 


EX (SP),IY 


0476 


ED7B8405 


608 


LD SP,(NN) 


0502 


FDE5 


661 


PUSH IY 


047A 


EDAO 


609 


LDI 


0504 


FDE9 


662 


JP (IY) 


047C 


EDA1 


610 


CPI 


0506 


FDF9 


663 


LD SP.IY 


047E 


EDA2 


611 


INI 


0508 


FDCB0506 


664 


RLC (IY + IND) 


0480 


EDA3 


612 


OUTI 


050C 


FDCB050E 


665 


RRCUY + IND) 


0482 


EDA8 


613 


LDD 


0510 


FDCB0516 


666 


RL(IY + IND) 


0484 


EDA9 


614 


CPD 


0514 


FDCB051E 


667 


RR(IY + IND) 


0486 


EDAA 


615 


IND 


0518 


FDCB0526 


668 


SLA(IY + IND) 


0488 


EDAB 


616 


OUTD 


051C 


FDCB052E 


669 


SRA(IY + IND) 


048A 


EDBO 


617 


LDIR 


0520 


FDCB053E 


670 


SRL(IY + IND) 


048C 


EDB1 


618 


CPIR 


0524 


FDCB0546 


671 


BIT0,(IY + IND) 


048E 


EDB2 


619 


INIR 


0528 


FDCB054E 


672 


BIT1,(IY + IND) 


0490 


EDB3 


620 


OTIR 


052C 


FDCB0556 


673 


BIT2,(IY + IND) 


0492 


EDB8 


621 


LDDR 


0530 


FDCB055E 


674 


BIT3,(IY + IND) 


0494 


EDB9 


622 


CPDR 


0534 


FDCB0566 


675 


BIT4,(IY + IND) 


0496 


EDBA 


623 


INDR 


0538 


FDCB056E 


676 


BIT5,(IY + IND) 


0498 


EDBB 


624 


OTDR 


053C 


FDCB0576 


677 


BIT6,(IY + IND) 


049A 


FD09 


625 


ADD IY.BC 


0540 


FDCB057E 


678 


BIT7,(IY + IND) 


049C 


FD19 


626 


ADD IY.DE 


0544 


FDCB0586 


679 


RES0,(IY + IND) 


049E 


FD2 18405 


627 


LD IY.NN 


0548 


FDCB058E 


680 


RESi,(IY + IND) 


04A2 


FD228405 


628 


LD (NN),IY 


054C 


FDCB0596 


681 


RES2,(IY + IND) 


04A6 


FD23 


629 


INCIY 


0550 


FDCB059E 


682 


RES3,(IY + IND) 


04A8 


FD29 


630 


ADD IY.IY 


0554 


FDCB05A6 


683 


RES4,(IY + IND) 


04AA 


FD2A8405 


631 


LD IY.(NN) 


0558 


FDCB05AE 


684 


RES5,(IY + IND) 


04AE 


FD2B 


632 


DECIY 


055C 


FDCB05B6 


685 


RES6,(IY + IND) 


04B0 


FD3405 


633 


INC0Y + IND) 


0560 


FDCB05BE 


686 


RES7,(IY + IND) 


04B3 


FD3505 


634 


DEC(IY + IND) 


0564 


FDCB05C6 


687 


SET0,(IY + IND) 


04B6 


FD360520 


635 


LD(IY + IND),N 


0568 


FDCB05CE 


688 


SET1,(IY + IND) 


04BA 


FD39 


636 


ADD IY,SP 


056C 


FDCB05D6 


689 


SET2,(IY + IND) 


04BC 


FD4605 


637 


LDB,(IY + IND) 


0570 


FDCB05DE 


690 


SET3,(IY + IND) 


04BF 


FD3E05 


638 


LDC,(IY + IND) 


0574 


FDCB05E6 


691 


SET4,(IY + IND) 


04C2 


FD5605 


639 


LDD,(IY + IND) 


0578 


FDCB05EE 


692 


SET5,(IY + IND) 


04C5 


FD5E05 


640 


LDE,(IY + IND) 


057C 


FDCB05F6 


693 


SET6,(IY + IND) 


04C8 


FD6605 


641 


LDH,(IY + IND) 


0580 


FDCB05FE 


694 


SET7,(IY + IND) 


04CB 


FD6E05 


642 


LDL,(IY + IND) 


0584 




695 NN 


DEFS 2 


04CE 


FD7005 


643 


LD(IY + IND),B 






696 IND 


EQU5 


04D1 


FD7105 


644 


LD(IY + IND),C 






697 M 


EQU 10H 


04D4 


FD7205 


645 


LD(IY + IND),D 






698 N 


EQU 20H 


04D7 


FD7305 


646 


LD(IY + IND),E 






699 DIS 


EQU 30H 


04DA 


FD7405 


647 


LD(IY + IND),H 






700 


END 



239 



SERIES I EDITOR/ASSEMBLER 






Appendix E/Alphabetic List of Instruction Set 

Following is an alphabetical listing of the nmemonic or source statement in column four. The object code is 
shown in column two. 



LOC 


OBJ CODE 


STMT 


SOURCE STATEMENT 


LOC 


OBJ CODE 


STMT 


1 


SOURCE STATEMENT 


0000 


8E 


1 


ADC 


A,(HL) 


005C 


CB42 


56 


BIT 


0,D 


0001 


DD8E05 


? 


ADC 


A, (IX + IND) 


005E 


CB43 


57 


BIT 


0,E 


0004 


FD8E05 


3 


ADC 


A,(IY + IND) 


0060 


CB44 


58 


BIT 


0,H 


0007 


8F 


4 


ADC 


A,A 


0062 


CB45 


59 


BIT 


0,L 


0008 


88 


5 


ADC 


A.B 


0064 


CB4E 


60 


BIT 


l.(HL) 


0009 


89 


6 


ADC 


A,C 


0066 


DDCB054E 


61 


BIT 


1, (IX + IND) 


000A 


8A 


7 


ADC 


A,D 


006A 


FDCB054E 


62 


BIT 


1, (IY + IND) 


000B 


8B 


8 


ADC 


A,E 


006E 


CB4F 


63 


BIT 


l.A 


oooc 


8C 


9 


ADC 


A,H 


0070 


CB48 


64 


BIT 


l,B 


000D 


8D 


10 


ADC 


A.L 


0072 


CB49 


65 


BIT 


l.C 


000E 


CE20 


11 


ADC 


A.N 


0074 


CB4A 


66 


BIT 


ID 


0010 


ED4A 


12 


ADC 


HL.BC 


0076 


CB4B 


67 


BIT 


1,E 


0012 


ED5A 


13 


ADC 


HL.DE 


0078 


CB4C 


68 


BIT 


1,H 


0014 


ED6A 


14 


ADC 


HL.HL. 


007A 


CB4D 


69 


BIT 


1,L 


0016 


ED7A 


15 


ADC 


HL.SP 


007C 


CB56 


70 


BIT 


2,(HL.) 


0018 


86 


16 


ADD 


A,(HL) 


007E 


DDCB0556 


71 


BIT 


2,(IX + IND) 


0019 


DD8605 


17 


ADD 


A,(IX + IND) 


0082 


FDCB0556 


72 


BIT 


2,(IY + IND) 


001C 


FD8605 


18 


ADD 


A,(IY + IND) 


0086 


CB57 


73 


BIT 


2,A 


001F 


87 


19 


ADD 


A.A 


0088 


CB50 


74 


BIT 


2,B 


0020 


80 


20 


ADD 


A,B 


008A 


CB51 


75 


BIT 


2,C 


0021 


81 


21 


ADD 


A,C 


008C 


CB52 


76 


BIT 


2,D 


0022 


82 


22 


ADD 


A.D 


008E 


CB53 


77 


BIT 


2,E 


0023 


83 


23 


ADD 


A,E 


0090 


CB54 


78 


BIT 


2,H 


0024 


84 


24 


ADD 


A,H 


0092 


CB55 


79 


BIT 


2,L 


0025 


85 


25 


ADD 


A,L 


0094 


CB5E 


80 


BIT 


3,(HL) 


0026 


C620 


26 


ADD 


A,N 


0096 


DDCB055E 


81 


BIT 


3,(IX + IND) 


0028 


09 


27 


ADD 


HL.BC 


009A 


FDCB055E 


82 


BIT 


3,(IY + IND) 


0029 


19 


28 


ADD 


HL.DE 


009E 


CB5F 


83 


BIT 


3,A 


002A 


29 


29 


ADD 


HL.HL 


00A0 


CB58 


84 


BIT 


3,B 


002B 


39 


30 


ADD 


HL.SP 


00A2 


CB59 


85 


BIT 


3,C 


002C 


DD09 


31 


ADD 


IX.BC 


00A4 


CB5A 


86 


BIT 


3,D 


002E 


DD19 


32 


ADD 


IX, DE 


00A6 


CB5B 


87 


BIT 


3,E 


0030 


DD29 


33 


ADD 


IX, IX 


00A8 


CB5C 


88 


BIT 


3,H 


0032 


DD39 


34 


ADD 


IX.SP 


00AA 


CB5D 


89 


BIT 


3,L 


0034 


FD09 


35 


ADD 


IY.BC 


00AC 


CB66 


90 


BIT 


4,(HL) 


0036 


FD19 


36 


ADD 


IY.DE 


00AE 


DDCB0566 


91 


BIT 


4,(IX + IND) 


0038 


FD29 


37 


ADD 


IY.IY 


00B2 


FDCB0566 


92 


BIT 


4.0Y + IND) 


003A 


FD39 


38 


ADD 


IY.SP 


00B6 


CB67 


93 


BIT 


4,A 


003C 


A6 


39 


AND 


(HL) 


00B8 


CB60 


94 


BIT 


4,B 


003D 


DDA605 


40 


AND 


(IX + IND) 


00BA 


CB61 


95 


BIT 


4,C 


0040 


FDA605 


41 


AND 


(IY + IND) 


00BC 


CB62 


96 


BIT 


4,D 


0043 


A7 


42 


AND 


A 


00BE 


CB63 


97 


BIT 


4,E 


0044 


A0 


43 


AND 


B 


ooco 


CB64 


98 


BIT 


4.H 


0045 


Al 


44 


AND 


C 


00C2 


CB65 


99 


BIT 


4,L 


0046 


A2 


45 


AND 


D 


00C4 


CB6E 


100 


BIT 


5,(HL) 


0047 


A3 


46 


AND 


E 


00C6 


DDCB056E 


101 


BIT 


5,(IX + IND) 


0048 


A4 


47 


AND 


H 


00CA 


FDCB056E 


102 


BIT 


5,(IY + IND) 


0049 


A5 


48 


AND 


L 


00CE 


CB6F 


103 


BIT 


5, A 


004A 


E620 


49 


AND 


N 


00D0 


CB68 


104 


BIT 


5,B 


004C 


CB46 


50 


BIT 


O.(HL) 


00D2 


CB69 


105 


BIT 


5,C 


004E 


DDCB0546 


51 


BIT 


0,(IX + IND) 


00D4 


CB6A 


106 


BIT 


5,D 


0052 


FDBC0546 


52 


BIT 


0.(IY + IND) 


0OD6 


CB6B 


107 


BIT 


5,E 


0056 


CB47 


53 


BIT 


0.A 


00D8 


CB6C 


108 


BIT 


5,H 


0058 


CB40 


54 


BIT 


0,B 


00DA 


CB6D 


109 


BIT 


5,L 


005A 


CB41 


55 


BIT 


0,C 


00DC 


CB76 


110 


BIT 


6,(HL) 



240 



APPENDIX 



LOC 


OBJ CODE 


STMT 


SOURCE STATEMENT 


OODE 


DDCB0576 


111 


BIT 


6,(IX + IND) 


00E2 


FDCB0576 


112 


BIT 


6.0Y + IND) 


00E6 


CB77 


113 


BIT 


6,A 


00E8 


CB70 


114 


BIT 


6,B 


OOEA 


CB71 


115 


BIT 


6.C 


OOEC 


CB72 


116 


BIT 


6,D 


OOEE 


CB73 


117 


BIT 


6,E 


00F0 


CB74 


118 


BIT 


6,H 


O0F2 


CB75 


119 


BIT 


6.L 


00F4 


CB7E 


120 


BIT 


7,(HL) 


00F6 


DDCB057E 


121 


BIT 


7,(IX + IND) 


OOFA 


FDCB057E 


122 


BIT 


7,(IY + IND) 


OOFE 


CB7F 


123 


BIT 


7,A 


OIOO 


CB78 


124 


BIT 


7.B 


0102 


CB79 


125 


BIT 


7.C 


0104 


CB7A 


126 


BIT 


7.D 


0106 


CB7B 


127 


BIT 


7,E 


0108 


CB7C 


128 


BIT 


7,H 


010A 


CB7D 


129 


BIT 


7,L 


010C 


DC8405 


130 


CALL 


CNN 


010F 


FC8405 


131 


CALL 


M.NN 


0112 


D48405 


132 


CALL 


NC.NN 


0115 


CD8405 


133 


CALL 


NN 


0118 


C48405 


134 


CALL 


NZ.NN 


01 IB 


F48405 


135 


CALL 


P,NN 


01 IE 


EC8405 


136 


CALL 


PE.NN 


0121 


E48405 


137 


CALL 


PO.NN 


0124 


CC8405 


138 


CALL 


Z.NN 


0127 


3F 


139 


CCF 




0128 


BE 


140 


CP 


(HL) 


0129 


DDBE05 


141 


CP 


(IX + IND) 


0I2C 


FDBE05 


142 


CP 


(IY + IND) 


012F 


BF 


143 


CP 


A 


0130 


B8 


144 


CP 


B 


0131 


B9 


145 


CP 


C 


0132 


BA 


146 


CP 


D 


0133 


BB 


147 


CP 


E 


0134 


BC 


148 


CP 


H 


0135 


BD 


149 


CP 


L 


0136 


FE20 


150 


CP 


N 


0138 


EDA9 


151 


CPD 




013A 


EDB9 


152 


CPDR 




013C 


EDA1 


153 


CPI 




013E 


EDB1 


154 


CPIR 




0140 


2F 


155 


CPL 




0141 


27 


156 


DAA 




0142 


35 


157 


DEC 


(HL) 


0143 


DD3505 


158 


DEC 


(IX + IND) 


0146 


FD3505 


159 


DEC 


(IY + IND) 


0149 


3D 


160 


DEC 


A 


014A 


05 


161 


DEC 


B 


014B 


OB 


162 


DEC 


BC 


014C 


OD 


163 


DEC 


C 


014D 


15 


164 


DEC 


D 


014E 


IB 


165 


DEC 


DE 


014F 


ID 


166 


DEC 


E 


0150 


25 


167 


DEC 


H 


0151 


2B 


168 


DEC 


HL 


0152 


DD2B 


169 


DEC 


IX 


0154 


FD2B 


170 


DEC 


IY 


0156 


2D 


171 


DEC 


L 



LOC 


OBJ CODE 


STMT 


SOURCE STATEM 


0157 


3B 


172 


DEC 


SP 


0158 


F3 


173 


DI 




0159 


102E 


174 


DJNZ 


DIS 


015B 


FB 


175 


EI 




015C 


E3 


176 


EX 


(SP).HL 


015D 


DDE3 


177 


EX 


(SP).IX 


015F 


FDE3 


178 


EX 


(SP).IY 


0161 


08 


179 


EX 


AF.AF' 


0162 


EB 


180 


EX 


DE.HL 


0163 


D9 


181 


EXX 




0164 


76 


182 


HALT' 




0165 


ED46 


183 


IM 





0167 


ED56 


184 


IM 


1 


0169 


ED5E 


185 


IM 


2 


016B 


ED78 


186 


IN 


A.(C) 


016D 


DB20 


187 


IN 


A,N 


016F 


ED40 


188 


IN 


B,(C) 


0171 


ED48 


189 


IN 


C(C) 


0173 


ED50 


190 


IN 


D.(C) 


0175 


ED58 


191 


IN 


E,(C) 


0177 


ED60 


192 


IN 


H,(C) 


0179 


ED68 


193 


IN 


L,(C) 


017B 


34 


194 


INC 


(HL) 


0I7C 


DD3405 


195 


INC 


(IX + IND) 


017F 


FD3405 


196 


INC 


(IY + IND) 


0182 


3C 


197 


INC 


A 


0183 


04 


198 


INC 


B 


0184 


03 


199 


INC 


BC 


0185 


OC 


200 


INC 


C 


0186 


14 


201 


INC 


D 


0187 


13 


202 


INC 


DE 


0188 


1C 


203 


INC 


E 


0189 


24 


204 


INC 


H 


018A 


23 


205 


INC 


HL 


018B 


DD23 


206 


INC 


IX 


018D 


FD23 


207 


INC 


IY 


018F 


2C 


208 


INC 


L 


0190 


33 


209 


INC 


SP 


0191 


EDAA 


210 


IND 




0193 


EDBA 


211 


INDR 




0195 


EDA2 


212 


INI 




0197 


EDB2 


213 


IN1R 




0199 


E9 


214 


JP 


(HL) 


019A 


DDE9 


215 


JP 


(IX) 


019C 


FDE9 


216 


JP 


(IY) 


019E 


DA8405 


217 


JP 


CNN 


01A1 


FA8405 


218 


JP 


M.NN 


01A4 


D28405 


219 


JP 


NCNN 


01A7 


C38405 


220 


JP 


NN 


01AA 


C28405 


221 


JP 


NZ.NN 


01AD 


F28405 


222 


JP 


P,NN 


01B0 


EA8405 


223 


JP 


PE.NN 


01B3 


E28405 


224 


JP 


PO.NN 


01B6 


CA8405 


225 


JP 


Z.NN 


01B9 


382E 


226 


JR 


GDIS 


01BB 


182E 


227 


JR 


DIS 


01BD 


302E 


228 


JR 


NC.DIS 


01BF 


202E 


229 


JR 


NZ.DIS 


01C1 


282E 


230 


JR 


Z.DIS 


01C3 


02 


231 


LD 


(BC).A 


01C4 


12 


232 


LD 


(DE),A 



241 



SERIES I EDITOR/ASSEMBLER 



LOC 


OBJ CODE 


STMT 




SOURCE STATEMENT 


LOC 


OBJ CODE 


sTMT 




SOURCE STATEMENT 


01C5 


77 


233 


LD 


(HL),A 


024C 


FD4E05 


294 


LD 


C,(IY + IND) 


0IC6 


70 


234 


LD 


(HL.),B 


024F 


4F 


295 


LD 


C.A 


0IC7 


71 


235 


L.D 


(HL),C 


0250 


48 


296 


L.D 


C,B 


01C8 


72 


236 


LD 


(HL),D 


0251 


49 


297 


LD 


C.C 


0IC9 


73 


237 


LD 


(HL),E 


0252 


4A 


298 


LD 


CD 


01CA 


74 


238 


LD 


(HL),H 


0253 


4B 


299 


LD 


C.E 


01CB 


75 


239 


LD 


(HL),L 


0254 


4C 


WO 


LD 


C.H 


01CC 


3620 


240 


LD 


(HL).N 


0255 


4D 


101 


LD 


C,L 


01CE 


DD7705 


241 


LD 


(IX + 1NDJ.A 


0256 


0E20 


102 


LD 


C.N 


01DI 


DD7005 


242 


LD 


(1X + 1ND).B 


0258 


56 


103 


LD 


D,(HL) 


01D4 


DD7105 


243 


LD 


(IX + IND),C 


0259 


DD5605 


104 


LD 


D,(1X + 1ND) 


0ID7 


DD7205 


244 


LD 


(IX + IND),,D 


025C 


FD5605 


105 


LD 


D,(IY + IND) 


OIDA 


DD7305 


245 


LD 


(IX + 1ND1.E 


025F 


57 


106 


LD 


D.A 


OIDD 


DD7405 


246 


LD 


(IX + IND1.H 


0260 


50 


107 


LD 


D.B 


01E0 


DD7505 


247 


LD 


(IX + IND),L 


0261 


51 


108 


LD 


D.C 


01 E3 


DD360520 


248 


LD 


(1X + 1ND).N 


0262 


52 


109 


LD 


D.D 


01E7 


FD7705 


249 


LD 


(IY + 1ND),A 


0263 


53 


110 


LD 


D.E 


OIEA 


FD7005 


250 


LD 


(1Y + IND).B 


0264 


54 


111 


LD 


D.H 


01 ED 


FD7105 


251 


LD 


(IY + IND),C 


0265 


55 


112 


LD 


D.L 


01FO 


FD7205 


252 


LD 


(IY + 1ND).D 


0266 


1620 


113 


LD 


D.N 


01F3 


FD7305 


253 


LD 


(IY + 1ND),E 


0268 


ED5B8405 


114 


LD 


DE,(NN) 


01F6 


FD7405 


254 


LD 


(IY + INDU-I 


026C 


118405 


115 


LD 


DE.NN 


0IF9 


FD7505 


255 


LD 


(IY + IND),L 


026F 


5E 


116 


LD 


E,(HL) 


01 FC 


FD360520 


256 


LD 


(IY + IND),N 


0270 


DD5E05 


117 


LD 


E,(IX + IND) 


0200 


328405 


257 


LD 


(NN).A 


0273 


FD5E05 


118 


LD 


E,(IY + 1ND) 


0203 


ED438405 


258 


LD 


(NN),BC 


0276 


5F 


119 


LD 


E.A 


0207 


ED538405 


259 


LD 


(NN).DE 


0277 


58 


120 


LD 


E,B 


020B 


228405 


260 


LD 


(NN).HL 


0278 


59 


121 


LD 


E.C 


020E 


DD228405 


261 


LD 


(NN)JX 


0279 


5A 


122 


LD 


E.D 


0202 


FD228405 


262 


LD 


(NN)JY 


027A 


5B 


123 


LD 


E,E 


0216 


ED738405 


263 


LD 


(NN).SP 


027B 


5C 


124 


LD 


E,H 


021A 


OA 


264 


LD 


A,(BC) 


027C 


5D 


125 


LD 


E.L 


021 B 


1A 


265 


LD 


A.(DE) 


027D 


1E20 


126 


LD 


E.N 


021C 


7E 


266 


LD 


A.(HL) 


027F 


66 


127 


LD 


H,(HL) 


02 ID 


DD7E05 


267 


LD 


A,(IX + IND) 


0280 


DD6605 


128 


LD 


H.OX + IND) 


0220 


FD7E05 


268 


LD 


A,(IY + IND) 


0283 


FD6605 


129 


LD 


H,(IY + IND) 


0223 


3A8405 


269 


LD 


A,(NN) 


0286 


67 


130 


LD 


H,A 


0226 


7F 


270 


LD 


A,A 


0287 


60 


131 


LD 


H.B 


0227 


78 


271 


LD 


A.B 


0288 


61 


132 


LD 


H.C 


0228 


79 


272 


LD 


A.C 


0289 


62 


133 


LD 


H.D 


0229 


7A 


273 


LD 


A.D 


028A 


63 


134 


LD 


H.E 


022A 


7B 


274 


LD 


A.E 


028B 


64 


135 


LD 


H.H 


022B 


7C 


275 


LD 


A,H 


028C 


65 


136 


LD 


H,L 


022C 


ED57 


276 


LD 


A.I 


028D 


2620 


137 


LD 


H.N 


022E 


7D 


277 


LD 


A.L 


028F 


2A8405 


138 


LD 


HL.(NN) 


022F 


3E20 


278 


LD 


A,N 


0292 


218405 


139 


LD 


HL.NN 


0231 


46 


279 


LD 


B.(HL) 


0295 


ED47 


140 


LD 


LA 


0232 


DD4605 


280 


LD 


B,(IX + 1ND) 


0297 


DD2A8405 


141 


LD 


IX.(NN) 


0235 


FD4605 


281 


LD 


B,(IY + 1ND) 


029B 


DD2 18405 


142 


LD 


IX.NN 


0238 


47 


282 


LD 


B,A 


029F 


FD2A8405 


143 


LD 


IY.(NN) 


0239 


40 


283 


LD 


B,B 


02A3 


FD2 18405 


144 


LD 


1Y.NN 


023A 


41 


284 


LD 


B,C 


02A7 


6E 


145 


LD 


L,(HL) 


023B 


42 


285 


LD 


B,D 


02A8 


DD6E05 


146 


LD 


L,(IX + 1N'D) 


023C 


43 


286 


LD 


B,E 


02 A B 


FD6E05 


147 


LD 


L.UY + IND) 


023D 


44 


287 


LD 


B,H 


02AE 


6F 


148 


LD 


L.A 


023E 


45 


288 


LD 


B,L 


02AF 


68 


149 


LD 


L„B 


023F 


0620 


289 


LD 


B,N 


02B0 


69 


150 


LD 


L.C 


0241 


ED4B8405 


290 


LD 


BC.(NN) 


02B1 


6A 


151 


LD 


L.D 


0245 


018405 


291 


LD 


BC.NN 


02B2 


6B 


152 


LD 


L.E 


0248 


4E 


292 


LD 


C(HL) 


02B3 


6C 


153 


LD 


L.H 


0249 


DD4E05 


293 


LD 


C,(IX + IND) 


02B4 


6D 


154 


LD 


L.L 



242 



APPENDIX 



LOC 


OBJ CODE 


STMT 


SOURCE STATEMENT 


02B4 


6D 


354 


LD 


L.L 


02B5 


2E20 


355 


LD 


L,N 




ED4F 




LD 


R.A 


02B7 


ED7B8405 


356 


LD 


SP.(NN) 


02BB 


F9 


357 


LD 


SP.HL 


02BC 


DDF9 


358 


LD 


SP.1X 


02BE 


FDF9 


359 


LD 


SP.1Y 


02C0 


318405 


360 


LD 


SP.NN 


02C3 


EDA8 


361 


LDD 




02C5 


EDB8 


362 


LDDR 




02C7 


EDAO 


363 


LDI 




02C9 


EDBO 


364 


LDIR 




02CB 


ED44 


365 


NEG 




02CD 


00 


366 


NOP 




02CE 


B6 


367 


OR 


(HL) 


02CF 


DDB605 


368 


OR 


(IX + 1ND) 


02D2 


FDB605 


369 


OR 


(IY + IND) 


02D5 


B7 


370 


OR 


A 


02D6 


B0 


371 


OR 


B 


02D7 


Bl 


372 


OR 


C 


02D8 


B2 


373 


OR 


D 


02D9 


B3 


374 


OR 


E 


02DA 


B4 


375 


OR 


H 


02DB 


B5 


376 


OR 


L 


02DC 


F620 


377 


OR 


N 


02DE 


ED8B 


378 


OTDR 




02E0 


EDB3 


379 


OTIR 




02E2 


ED79 


380 


OUT 


(C).A 


02E4 


ED41 


381 


OUT 


(C).B 


02E6 


ED49 


382 


OUT 


(C),C 


02E8 


ED51 


383 


OUT 


(C),D 


02EA 


ED59 


384 


OUT 


(C),E 


02EC 


ED6I 


385 


OUT 


(C).H 


02EE 


ED69 


386 


OUT 


(C),L 


02FO 


D320 


387 


OUT 


N.A 


02F2 


EDAB 


388 


OUTD 




02F4 


EDA3 


389 


OUTI 




02F6 


Fl 


390 


POP 


AF 


02F7 


CI 


391 


POP 


BC 


02F8 


Dl 


392 


POP 


DE 


02F9 


El 


393 


POP 


HL 


02FA 


DDE1 


394 


POP 


IX 


02FC 


FDE1 


395 


POP 


IY 


02FE 


F5 


396 


PUSH 


AF 


02FF 


C5 


397 


PUSH 


BC 


0300 


D5 


398 


PUSH 


DE 


0301 


E5 


399 


PUSH 


HL 


0302 


DDE5 


400 


PUSH 


IX 


0304 


FDE5 


401 


PUSH 


IY 


0306 


CB86 


402 


RES 


0,(HL) 


0308 


DDCB0586 


403 


RES 


0,(IX + IND) 


030C 


FDCB0586 


404 


RES 


0,(IY + IND) 


0310 


CB87 


405 


RES 


0,A 


0312 


CB80 


406 


RES 


0,B 


0314 


CB81 


407 


RES 


o,c 


0316 


CB82 


408 


RES 


0,D 


0318 


CB83 


409 


RES 


0,E 


03IA 


CB84 


410 


RES 


0,H 


03 1C 


CB85 


411 


RES 


0,L 


031E 


CB8E 


412 


RES 


1,(HL) 


0320 


DDCB058E 


413 


RES 


1,(IX + IND) 



LOC 


OBJ CODE 


STMT 


SOU 


RCE STATEMI 


0324 


FDCB058E 


414 


RES 


1,(IY + IND) 


0328 


CB8F 


415 


RES 


l.A 


032A" 


CB88 


416 


RES 


l.B 


032C 


CB89 


417 


RES 


IX 


032E 


CB8A 


418 


RES 


l.D 


0330 


CB8B 


419 


RES 


l.E 


0332 


CB8C 


420 


RES 


I.H 


0334 


CB8D 


421 


RES 


IX 


0336 


CB96 


422 


RES 


2,(HL) 


0338 


DDCB0596 


423 


RES 


2.0X + IND) 


033C 


FDCB0596 


424 


RES 


2,(1Y + 1ND) 


0340 


CB97 


425 


RES 


2,A 


0342 


CB90 


426 


RES 


2,B 


0344 


CB91 


427 


RES 


2X 


0346 


CB92 


428 


RES 


2.D 


0348 


CB93 


429 


RES 


2,E 


034A 


CB94 


430 


RES 


2.H 


034C 


CB95 


431 


RES 


2X 


034E 


CB9E 


432 


RES 


3.(HL) 


0350 


DDCB059E 


433 


RES 


3,(IX + IND) 


0354 


FDCB059E 


434 


RES 


3.(IY + 1ND) 


0358 


CB9F 


435 


RES 


3, A 


035A 


CB98 


436 


RES 


3,B 


035C 


CB99 


437 


RES 


3X 


035E 


CB9A 


438 


RES 


3.D 


0360 


CB9B 


439 


RES 


3.E 


0362 


CB9C 


440 


RES 


3,H 


0364 


CB9D 


441 


RES 


3X 


0366 


CBA6 


442 


RES 


4,(HL) 


0368 


DDCB05A6 


443 


RES 


4.0X + IND) 


036C 


FDCB05A6 


444 


RES 


4,(1Y + IND) 


0370 


CBA7 


445 


RES 


4,A 


0372 


CBA0 


446 


RES 


4,B 


0374 


CBA1 


447 


RES 


4X 


0376 


CBA2 


448 


RES 


4,D 


0378 


CBA3 


449 


RES 


4,E 


037A 


CBA4 


450 


RES 


4,H 


037C 


CBA5 


451 


RES 


4,L 


037E 


CBAE 


452 


RES 


5,(HL) 


0380 


DDCB05AE 


453 


RES 


5,(IX + 1ND) 


0384 


FDCB05AE 


454 


RES 


5,(IY + 1ND) 


0388 


CBAF 


455 


RES 


5,A 


038A 


CBA8 


456 


RES 


5,B 


038C 


CBA9 


457 


RES 


5X 


038E 


CBAA 


458 


RES 


5,D 


0390 


CBAB 


459 


RES 


5,E 


0392 


CBAC 


460 


RES 


5,H 


0394 


CBAD 


461 


RES 


5X 


0396 


CBB6 


462 


RES 


6,(HL) 


0398 


DDCB05B6 


463 


RES 


6,(1X + IND) 


039C 


FDCB05B6 


464 


RES 


6.UY + IND) 


03A0 


CBB7 


465 


RES 


6,A 


03A2 


CBB0 


466 


RES 


6.B 


03A4 


CBB1 


467 


RES 


6,C 


03A6 


CBB2 


468 


RES 


6,D 


03A8 


CBB3 


469 


RES 


6,E 


03AA 


CBB4 


470 


RES 


6,H 


03AC 


CBB5 


471 


RES 


6X 


03AE 


CBBE 


472 


RES 


7,(HL) 


03B0 


DDCB05BE 


473 


RES 


7,(IX + IND) 


03B4 


FDCB05BE 


474 


RES 


7,(1Y + 1ND) 



243 



SERIES 1 EDITOR/ASSEMBLER 



LOC 


OBJ CODE 


STMT 


SOURCE STATEM 


03B8 


CBBF 


475 


RES 


7, A 


03BA 


CBB8 


476 


RES 


7,B 


03BC 


CBB9 


477 


RES 


7,C 


03BE 


CBBA 


478 


RES 


7,D 


03C0 


CBBB 


479 


RES 


7.E 


03C2 


CBBC 


480 


RES 


7,H 


03C4 


CBBD 


481 


RES 


7,L 


03C6 


C9 


482 


RET 




03C7 


D8 


483 


RET 


C 


03C8 


F8 


484 


RET 


M 


03C9 


DO 


485 


RET 


NC 


03CA 


CO 


486 


RET 


NZ 


03CB 


FO 


487 


RET 


P 


03CC 


E8 


488 


RET 


PE 


03CD 


EO 


489 


RET 


PO 


03CE 


C8 


490 


RET 


Z 


03CF 


ED4D 


491 


RETI 




03D1 


ED45 


492 


RETN 




03D3 


CBI6 


493 


RL 


(HL.) 


03D5 


DDCB05I6 


494 


RL 


(IX + 1ND) 


03D9 


FDCB0516 


495 


RL 


(1Y + 1ND) 


03DD 


CB17 


496 


RL 


A 


03DF 


CB10 


497 


RL 


B 


03EI 


CB11 


498 


RL 


C 


03E3 


CBI2 


499 


RL 


D 


03E5 


C8I3 


500 


RL 


E 


03E7 


CBI4 


501 


RL 


H 


03E9 


CBI5 


502 


RL 


L 


03EB 


17 


503 


RLA 




03EC 


CB06 


504 


RLC 


(HL) 


03EE 


DDCB0506 


505 


RLC 


(1X + 1ND) 


03F2 


FDCB0506 


506 


RLC 


(IY + IND) 


03F6 


CB07 


507 


RLC 


A 


03F8 


CB00 


508 


RLC 


B 


03FA 


CB01 


509 


RLC 


C 


03FC 


CB02 


510 


RLC 


D 


03FE 


CB03 


511 


RLC 


E 


0400 


CB04 


512 


RLC 


H 


0402 


CB05 


513 


RLC 


L. 


0404 


07 


514 


RLCA 




0405 


ED6F 


515 


RED 




0407 


CB1E 


516 


RR 


(HL) 


0409 


DDCB051E 


517 


RR 


(IY + IND) 


040D 


FDCB051E 


518 


RR 


(IY + IND) 


0411 


CB1F 


519 


RR 


A 


0413 


CB18 


520 


RR 


B 


0415 


CB19 


521 


RR 


C 


0417 


CB1A 


522 


RR 


D 


0419 


CBIB 


523 


RR 


E 


041B 


CB1C 


524 


RR 


H 


041D 


CB1D 


525 


RR 


L 


041F 


IF 


526 


RRA 




0420 


CB0E 


527 


RRC 


(HL) 


0422 


DDCB050E 


528 


RRC 


(IX + IND) 


0426 


FDCB050E 


529 


RRC 


(IY + IND) 


042A 


CB0F 


530 


RRC 


A 


042C 


CB08 


531 


RRC 


B 


042E 


CB09 


532 


RRC 


C 


0430 


CB0A 


533 


RRC 


D 


0432 


CB0B 


534 


RRC 


E 


0434 


CB0C 


535 


RRC 


H 



LOC 


OBJ CODE 


STf 


0436 


CB0D 


536 


0438 


OF 


537 


0439 


ED67 


538 


043B 


C7 


539 


043C 


D7 


540 


043D 


DF 


541 


043E 


E7 


542 


043F 


EF 


543 


0440 


F7 


544 


0441 


FF 


545 


0442 


CF 


546 


0443 


9E 


547 


0444 


DD9E05 


548 


0447 


FD9E05 


549 


044A 


9F 


550 


044B 


98 


551 


044C 


99 


552 


044D 


9A 


553 


044E 


9B 


554 


044F 


9C 


555 


0450 


9D 


556 


0451 


DE20 


557 


0453 


ED42 


558 


0455 


ED52 


559 


0457 


ED62 


560 


0459 


ED72 


561 


045B 


37 


562 


045C 


CBC6 


563 


045E 


DDCB05C6 


564 


0462 


FDCB05C6 


565 


0466 


CBC7 


566 


0468 


CBC0 


567 


046A 


CBC1 


568 


046C 


CBC2 


569 


046E 


CBC3 


570 


0470 


CBC4 


571 


0472 


CBC5 


572 


0474 


CBCE 


573 


0476 


DDCB05CE 


574 


047A 


FDCB05CE 


575 


047E 


CBCF 


576 


0480 


CBC8 


577 


0482 


CBC9 


578 


0484 


CBCA 


579 


0486 


CBCB 


580 


0488 


CBCC 


581 


048A 


CBCD 


582 


048C 


CBD6 


583 


048E 


DDCB05D6 


584 


0492 


FDCB05D6 


585 


0496 


CBD7 


586 


0498 


CBD0 


587 


049A 


CBD1 


588 


049C 


CBD2 


589 


049E 


CBD3 


590 


04A0 


CBD4 


591 


04A2 


CBD5 


592 


04A4 


CBD8 


593 


04A6 


CBDE 


594 


04A8 


DDCB05DE 


595 


04AC 


FDCB05DE 


596 



SOURCE STATEMENT 



RRC 


L 


RRCA 




RRD 




RST 





RST 


10H 


RST 


18H 


RST 


20H 


RST 


28H 


RST 


30H 


RST 


38H 


RST 


08H 


SBC 


A,(HL) 


SBC 


A,(IX + IND) 


SBC 


A,(IY + IND) 


SBC 


A,A 


SBC 


A,B 


SBC 


A,C 


SBC 


A,D 


SBC 


A,E 


SBC 


A,H 


SBC 


A,L 


SBC 


A,N 


SBC 


HL.BC 


SBC 


HL.DE 


SBC 


HL.HL 


SBC 


HL,SP 


SCF 




SET 


0,(HL) 


SET 


0,(IX + IND) 


SET 


0,(IY + IND) 


SET 


0,A 


SET 


0,B 


SET 


0,C 


SET 


0,D 


SET 


0,E 


SET 


0,H 


SET 


0,L 


SET 


l.(HL) 


SET 


UIX + 1ND) 


SET 


UTY + IND) 


SET 


1,A 


SET 


l.B 


SET 


l.C 


SET 


I.D 


SET 


1,E 


SET 


1,H 


SET 


1,L 


SET 


2,(HL) 


SET 


2,(IX + IND) 


SET 


2,(IY + IND) 


SET 


2,A 


SET 


2,B 


SET 


2,C 


SET 


2,D 


SET 


2,E 


SET 


2,H 


SET 


2,L 


SET 


3.B 


SET 


3,(HL) 


SET 


3,(IX + IND) 


SET 


3,(IY + IND) 



244 



«:.s,»gsais»t«gii»ia«aE 



APPENDIX 






fajt S lis ^^ 



LOC 


OBJ CODE 


STMT 




SOURCE STATEMENT 


04B4 


CBDA 


599 


SET 


3,D 


04B6 


CBDB 


600 


SET 


3,E 


04B8 


CBDC 


601 


SET 


3,H 


04BA 


CBDD 


602 


SET 


3,L 


04BC 


CBE6 


603 


SET 


4,(HL) 


04BE 


DDCB05E6 


604 


SET 


4,(IX + IND) 


04C2 


FDCB05E6 


605 


SET 


4,(IY + IND) 


04C6 


CBE7 


606 


SET 


4,A 


04C8 


CBEO 


607 


SET 


4,B 


04CA 


CBE1 


608 


SET 


4,C 


04CC 


CBE2 


609 


SET 


4,D 


04CE 


CBE3 


610 


SET 


4,E 


04D0 


CBE4 


611 


SET 


4,H 


Q4D2 


CBE5 


612 


SET 


4,L 


04D4 


CBEE 


613 


SET 


5,(HL) 


04D6 


DDCB05EE 


614 


SET 


5,(IX + IND) 


04DA 


FDCB05EE 


615 


SET 


5,(IY + IND) 


04DE 


CBEF 


616 


SET 


5, A 


04E0 


CBE8 


617 


SET 


5,B 


04E2 


CBE9 


618 


SET 


5,C 


04E4 


CBEA 


619 


SET 


5.D 


04E6 


CBEB 


620 


SET 


5,E 


04E8 


CBEC 


621 


SET 


5,H 


04EA 


CBED 


622 


SET 


5,L 


04EC 


CBF6 


623 


SET 


6,(HL) 


04EE 


DDCB05F6 


624 


SET 


6,(IX + IND) 


04F2 


FDCB05F6 


625 


SET 


6,(IY + IND) 


04F6 


CBF7 


626 


SET' 


6,A 


04F8 


CBFO 


627 


SET 


6,B 


04FA 


CBF1 


628 


SET 


6,C 


04FC 


CBF2 


629 


SET 


6,D 


04FE 


CBF3 


630 


SET 


6,E 


0.500 


CBF4 


631 


SET 


6,H 


0502 


CBF5 


632 


SET 


6,L 


0504 


CBFE 


633 


SET 


7,(HL) 


0506 


DDCB05FE 


634 


SET 


7,(1X + 1ND) 


050A 


FDCB05FE 


635 


SET 


7,(1Y + IND) 


050E 


CBFF 


636 


SET 


7,A 


0510 


CBF8 


637 


SET 


7,B 


0512 


CF9 


638 


SET 


7,C 


0514 


CBFA 


639 


SET 


7,D 


0516 


CBFB 


640 


SET 


7,E 


0518 


CBFC 


641 


SET 


7,H 


051A 


CBFD 


642 


SET 


7,L 


051C 


CB26 


643 


SLA 


(HL) 


05 IE 


DDCB0526 


644 


SLA 


(IX + IND) 


0522 


FDCB0526 


645 


SLA 


(IY + IND) 


0526 


CB27 


646 


SLA 


A 


0528 


CB20 


647 


SLA 


B 


052A 


CB21 


648 


SLA 


C 


052C 


CB22 


649 


SLA 


D 



LOC 


OBJ CODE 


STMT 




SOURCE STATEM 


052E 


CB23 


650 


SLA 


E 


0530 


CB24 


651 


SLA 


H 


0532 


CB25 


652 


SLA 


L 


0534 


CB2E 


653 


SRA 


(HL) 


0536 


DDCB052E 


654 


SRA 


(IX + IND) 


053A 


FDCB052E 


655 


SRA 


(IY + IND) 


053E 


CB2F 


656 


SRA 


A 


0540 


CB28 


657 


SRA 


B 


0542 


CB29 


658 


SRA 


C 


0544 


CB2A 


659 


SRA 


D 


0546 


CB2B 


660 


SRA 


E 


0548 


CB2C 


661 


SRA 


H 


054A 


CB2D 


662 


SRA 


L 


054C 


CB3E 


663 


SRL 


(HL) 


054E 


DDCB053E 


664 


SRL 


(IX + IND) 


0552 


FDCB053E 


665 


SRL 


(IY + IND) 


0556 


CB3F 


666 


SRL 


A 


0558 


CB38 


667 


SRL 


B 


055A 


CB39 


668 


SRL 


C 


055C 


CB3A 


669 


SRL 


D 


055E 


CB3B 


670 


SRL 


E 


0560 


CB3C 


671 


SRL 


H 


0562 


CB3D 


672 


SRL 


L 


0564 


96 


673 


SUB 


(HL) 


0565 


DD9605 


674 


SUB 


(IX + IND) 


0568 


FD9605 


675 


SUB 


(IY + IND) 


056B 


97 


676 


SUB 


A 


056C 


90 


677 


SUB 


B 


056D 


91 


678 


SUB 


C 


056E 


92 


679 


SUB 


D 


056F 


93 


680 


SUB 


E 


0570 


94 


681 


SUB 


H 


0571 


95 


682 


SUB 


L 


0572 


D620 


683 


SUB 


N 


0574 


AE 


684 


XOR 


(HL) 


0575 


DDAE05 


685 


XOR 


(IX + IND) 


0578 


FDAE05 


686 


XOR 


(IY + IND) 


057B 


AF 


687 


XOR 


A 


057C 


A8 


688 


XOR 


B 


057D 


A9 


689 


XOR 


C 


057E 


AA 


690 


XOR 


D 


057F 


AB 


691 


XOR 


E 


0580 


AC 


692 


XOR 


H 


0581 


AD 


693 


XOR 


L 


0582 


EE20 


694 


XOR 


N 


0584 




695 NN 


DEFS 


~2 






696 IND 


EQU 


5 






697 M 


EQU 


10H 






698 N 


EQU 


20H 






699 DIS 


EQU 


30H 






700 


END 





245 



SERIES i EDITOR/ASSEMBLER 



AppendIxF/Z-80 CPU Register and 
Architecture 

This section gives information about the actual Z80 chip including the Central 
Processing Unit (CPU) Register configuration. 

Z-80 CPU Architecture 

A block diagram of the internal architecture of the z-80 CPU is shown in Figure 
2. The diagram shows all of the major elements in the cpu and it should be 
referred to throughout the following description. 

CPU Registers 

The z-80 cpu contains 208 bits of r/w memory that are accessible to the 
programmer. Figure 3 illustrates how this memory is configured into eighteen 
8-bit registers and four 16-bit registers. All z-80 registers are implemented usin£ 
static ram. The registers include two sets of six general purpose registers that 
may be used individually as 8-bit registers or in pairs of 16-bit registers. There 
are also two sets of accumulator and flag registers. 

Special Purpose Registers 



I 8 BIT 
DATA BUS 



13 
CPU AND 
SYSTEM 
CONTROL 
SIGNALS 



INSTRUCTION 

DECODE 

& 

CPU 

CONTROL 



DATA BUS 
CONTROL 



INTERNAL DATA BUS 



CPU 
CONTROL 



C> ALU 



CPU 
REGISTERS 



AAA 



ADDRESS 
CONTROL 



16BIT 
ADDRESS BUS 



Figure 2, Z-80 CPU Block Diagram. 



246 



APPENDIX 



MAIN REG SET 
/S 



ALTERNATE REG SET 



ACCUMULATOR 
A 


FLAGS 
F 


ACCUMULATOR 
A' 


FLAGS 
F 


B 


C 


B' 


C 


D 


E 


D' 


E' 


H 


L 


H' 


L 



GENERAL 
> PURPOSE 
REGISTERS 



INTERRUPT 
VECTOR 



MEMORY 
REFRESH 
R 



INDEX REGISTER IX 



INDEX REGISTER IY 



STACK POINTER SP 



PROGRAM COUNTER PC 



SPECIAL 
y PURPOSE 
REGISTERS 



Figure 3, Z-80 CPU Register Configuration. 

1. Program Counter (PC). The program counter holds the 16-bit address of the 
current instruction being fetched from memory. The pc is automatically 
incremented after its contents have been transferred to the address lines. 
When a program jump occurs the new value is automatically placed in the pc, 
overriding the incrementer. 

2. Stack Pointer (SP). The stack pointer holds the 16-bit address of the current 
top of a stack located anywhere in external system ram memory. The 
external stack memory is organized as a last-in first-out (lifo) file. 

Data can be pushed onto the stack from specific CPU registers or popped off 
of the stack into specific CPU registers through the execution of push and pop 
instructions. The data popped from the stack is always the last data pushed 
onto it. The stack allows simple implementation of multiple level interrupts, 
unlimited subroutine nesting and simplification of many types of data 
manipulation. 

3. Two Index Register (ix & iy). The two independent index registers hold a 
16-bit base address that is used in indexed addressing modes. In this mode, 
an index register is used as a base to point to a region in memory from which 
data is to be stored or retrieved. An additional byte is included in indexed 
instructions to specify a displacement from this base. This displacement is 
specified as a two's complement signed integer. This mode of addressing 
greatly simplifies many types of programs, especially where tables of data 
are used. 



247 



SERI ES 1 EDITOR/ASSEMBLER 



4. Interrupt Page Address Register (i). The z-80 cpu can be operated in a 
mode where an indirect call to any memory location can be achieved in 
response to an interrupt. The i Register is used for this purpose to store the 
high order 8-bits of the indirect address while the interrupting device provides 
the lower 8-bits of the address. This feature allows interrupt routines to be 
dynamically located anywhere in memory with absolute minimal access time 
to the routine. 

5. Memory Refresh Register (r). The z-so cpu contains a memory refresh 
counter to enable dynamic memories to be used with the same ease as static 
memories. Seven bits of this 8 bit register are automatically incremented after 
each instruction fetch. The eighth bit will remain as programmed as the result 
of an L.D R, a instruction. The data in the refresh counter is sent out on the 
lower portion of the address bus along with a refresh control signal while the 
cpu is decoding and executing the fetched instruction. This mode of refresh is 
totally transparent to the programmer and does not slow down the cpu 
operation. The programmer can load the R register for testing purposes, but 
this register is normally not used by the programmer. During refresh, the 
contents of the i register are placed on the upper 8 bits of the address bus. 

Accumulator and Flag Registers 

The cpu includes two independent 8-bit accumulators and associated 8-bit flag 
registers. The accumulator holds the results of 8-bit arithmetic or logical 
operations while the flag register indicates specific conditions for 8 or 16-bit 
operations, such as indicating whether or not the result of an operation is equal 
to zero. The programmer selects the accumulator and flag pair that he wishes to 
work with a single exchange instruction so that he may easily work with either 
pair. 

General Purpose Registers 

There are two matched sets of general purpose registers, each set containing six 
8-bit registers that may be used individually as 8-bit registers or as 16-bit 
register pairs by the programmer. One set is called bc, de and hl while the 
complementary set is called bc; de and hl: At any one time the programmer 
can select either set of registers to work with through a single exchange 
command for the entire set. In systems where fast interrupt response is required, 
one set of general purpose registers and an accumulator/flag register may be 
reserved for handling this very fast routine. Only a simple exchange command 
need be executed to go between the routines. This greatly reduces interrupt 
service time by eliminating the requirement for saving and retrieving register 
contents in the external stack during interrupt or subroutine processing. These 
general purpose registers are used for a wide range of applications by the 
programmer. They also simplify programming, especially in ROM based systems 
where little external read/write memory is available. 



248 



APPENDIX 



Arithmetic & Logic Unit (ALU) 

The 8-bit arithmetic and logical instructions of the CPU are executed in the alu. 
Internally the alu communicates with the registers and the external data bus on 
the internal data bus. The type of functions performed by the alu include: 

Add Left or right shifts or rotates (arithmetic and logical) 

Subtract Increment 

Logical and Decrement 

Logical or Set bit 

Logical Exclusive or Reset bit 

Compare Test Bit 

Instruction Register and CPU Control 

As each instruction is fetched from memory, it is placed in the instruction 
register and decoded. The control sections performs this function and then 
generates and supplies all of the control signals necessary to read or write data 
from or to the registers, control the alu and provide all required external control 

signals. 

Z-80 CPU Pin Description 

The z-80 CPU is packaged in an industry standard 40 pin Dual In-Line Package. 
The i/o pins are shown in Figure 4 and the function of each is described below. 

A -A 15 Tri-state output, active high. A -A, 5 constitute a 16-bit 

(Address Bus) address bus. The address bus provides the address for 

memory (up to 64K bytes) data exchanges and for I/O 
device data exchanges. I/O addressing uses the 8 lower 
address bits to allow the user to directly select up to 256 
input or 256 output ports. A is the least significant address 
bit. During refresh time, the lower 7 bits contain a valid 
refresh address. 

D r D 7 Tri-state input/output, active high. D r D 7 constitute an 

(Data Bus) 8-bit bidirectional data bus. The data bus is used for data 

exchanges with memory and I/O devices. 

M] Output, active low. M, indicates that the current machine 

(Machine Cycle cycle is the OP code fetch cycle of an instruction execution, 
one) Note that during execution of 2-byte op-codes, M| is 

generated as each op-code byte is fetched. These two byte 
op-codes always begin with CBH, DDH, EDH or FDH. M, 
also occurs with IORQ to indicate an interrupt acknowledge 
cycle. 



249 



SERIES I EDITOR/ASSEMBLER 



SYSTEM 
CONTROL 



MREQ 
IORQ 



WR 
RFSH 



HALT 



CPU 
CONTROL 



> INT 



RESET 



( 



BUSRQ 



CPU 

BUS 

CONTROL 1 BUSAK 



+5V 
GND 



27 


Z- 80 CPU 


30 




31 




19 


32 


20 


33 




21 


34 




22 


35 




"* 


36 




28 


37 




4, 


38 




18 


39 




40 




24 


1 


ft. 


2 




16 


3 




17 


4 






5 _ 


26 


14 




25 




23 










15 




6 


12 
8 
7 




11 
29 Br 






9 






10 
13 











^11 

*12 

»14 
=■15 / 



\ DATA 
' BUS 



Figure 4, Z-80 Pin Configuration. 



MREQ 

(Memory 
Request) 



IORQ 

(Input/Output 
Request) 



RD 

(Memory Read) 



WR 

(Memory Write) 



Tri-state output, active low. The memory request signal 
indicates that the address bus holds a valid address for a 
memory read or memory write operation. 



Tri-state output, active low. The IORQ signal indicates that 
the lower half of the address bus hol ds a va lid I/O address 
for a I/O read or write operation. An IORQ signal is also 
generated with an M, signal when an interrupt is being 
acknowledged to indicate that an interrupt response vector 
can be placed on the data bus. Interrupt Acknowledge 
operations occur during M, time while I/O operations never 
occur during M) time. 

Tri-state output, active low. RD indicates that the CPU 
wants to read data from memory or an I/O device. The 
addressed I/O device or memory should use this signal to 
gate data onto the CPU data bus. 

Tri-state output, active low. WR indicates that the CPU data 
bus holds valid data to be stored in the addressed memory 
or I/O device . 



250 



APPENDIX 



RFSH 
(Refresh) 



HALT 
(Halt state) 



WAIT 

(Wait) 



INT 

(Interrupt 

Request) 



NMI 

(Non Maskable 

Interrupt) 



Output, active low. RFSH indicates that the lower 7 bits of 
the address bus contain a refresh address for dynamic 
memories and the current MREQ signal should be used to 
do a refresh read to all dynamic memories. 



Output, active low. HALT indicates that the CPU has 
executed a HALT software instruction and is awaiting either 
a non maskable or a maskable interrupt (with the mask 
enabled) before operation can resume. While halted, the 
CPU executes NOP's to maintain memory refresh activity. 



Input, active low. WAIT indicates to the Z-80 CPU that the 
addressed memory or I/O devices are not ready for a data 
transfer. The CPU continues to enter wait states for as long 
as this signal is active. This signal allows memory or I/O 
devices of any speed to be synchronized to the CPU. 

Input, active low. The Interrupt Request signal is generated 
by I/O devices. A request will be honored at the end of 
the current instruction if the internal software controlled 



interrupt enable flip-flop (IFF) is enabled and if the BUSRQ 
signal is not active. When t he CPU accepts the interrupt, an 
acknowledge signal (IORQ during M, time) is sent out at 
the beginning of the next instruction cycle. 

Input, negative edge triggered. The n on m askable interrupt 
request line has a higher priority than INT and is always 
recognized at the end of the current instructi on, in dependent 
of the status of the interrupt enable flip-flop. NMI 
automatically forces the Z-80 CPU to restart to location 
0066 H . The program counter is automatically saved in the 
external stack so that the user can return to the program that 
was interrupted. Note that continuous WAIT cycles can 
prevent t he current instr uction from ending, and that a 
BUSRQ will override a NMI. 



RESET 



Input, active low. RESET forces the program counter to 
zero and initializes the CPU. The CPU initialization 
includes: 

1) Disable the interrupt enable flip-flop 

2) Set Register I = 00 H 

3) Set Register R = 00 H 

4) Set Interrupt Mode 

During reset time, the address bus and data bus go to a high 
impedance state and all control output signals go to the 
inactive state. 



251 



SERIES I EDITOR/ASSEMBLER 



BUSRQ 

(Bus Request) 



BUSAK 

(Bus 

Acknowledge) 



O 



Input, active low. The bus request signal is used to request 
the CPU address bus, data bus and tri-state output control 
signals to go to a high impedan ce state so that other devices 
can control these buses. When BUSRQ is activated, the 
CPU will set these buses to a high impedance state as soon 
as the current CPU machine cycle is terminated. 

Output, active low. Bus acknowledge is used to indicate to 
the requesting device that the CPU address bus, data bus 
and tri-state control bus signals have been set to their high 
impedance state and the external device can now control 
these signals. 

Single phase TTL level clock which requires only a 330 
ohm pull-up resistor to + 5 volts to meet all clock 
requirements. 



Z-80 CPU Instruction Set 

The z-80 CPU can execute 158 different instruction types including all 78 of the 
8080A cpu. The instructions can be broken down into the following major 
groups: 

Load and Exchange 

• Block Transfer and Search 

• Arithmetic and Logical 

• Rotate and Shift 

Bit Manipulation (set, reset, test) 

• Jump, Call and Return 
Input/Output 

• Basic cpu Control 



252 



INDEX 



INDEX 



Subject Page 

Abbreviations 17 

Accumulator 248 

ADCA.S 109 

ADCHL.ss 142 

Add/Subtract flag 231 

ADDA.(HL) 107 

ADDA,(IX + d) 107 

ADDA.n 106 

ADDA.r .-.. 105 

ADDHL.ss 141 

ADDIX.pp 144 

ADDA,(IY + d) 108 

ADDIY.rr 145 

Alphabetical list of Z-80 

instructions 240-245 

ANDs 115 

Arithmetic logic unit (ALU) 249 

Assembler 21 

Commands 21 

Definitions 25-26 

Output 23 

Switch 21-22 

Using the assembler 21 

BITB.(HL) 178 

BITB,(IX + d) 179 

BITB,(IY + d) 180 

BITb.r 177 

CALL cc.nn 202 

CALL nn 201 

Carry flag 231 

CCF 134 

Central processing unit (CPU) 249 

Comments 26 

Computer Type 4 

CPD 102 

CPDR 103 

CPI 99 

CPIR 101 

CPL 132 

CPs 122 

CPU block diagram 246 

CPU — pin description 249-252 

Current line , 7 



Subject Page 

DAA 131 

DEC IX 149 

DECIY 149 

DECm 127 

DECss 148 

Dl 136 

DJNZe 199 

Editor 

Commands 8-1 5, 1 8, 1 9 

Definition 1 

Featuresof 2 

How to use 2, 5, 7 

El 137 

Error messages (assembler) 24-25 

Error messages (Editor) 16 

EXAF,AF' 87 

EXDE.HL 87 

Expressions 29 

EX(SP),HL 89 

EX(SP),IX 90 

EX(SP),IY 91 

EXX 88 

File 7 

Filename 7 

Flag register 248 

Flags(status) 231 

Half-Carry flag 232-233 

HALT 136 

IM0 138 

IM1 138 

IM2 139 

INA,(n) 211 

INC(HL) 125 

INCIX 146 

INC(IX-hd) 125 

INCIY 147 

INC(IY + d) 126 

INCr 124 

Increment '. . 7 

INCss 146 

IND 216 

Index registers 247 

INDR 217 



253 



SERIES I EDITOR/ASSEMBLER 



Subject Page 

INI 213 

INIR 214 

Input/Output commands 13 

IN r,(C) 212 

Interrupt register 248 

Italic type 4 

JPcc.nn 190 

JP(HL) 197 

JP(IX) 198 

JP(IY) 198 

JPnn 189 

JRC.e 192 

JRe 191 

JRNC.e 193 

JRNZ.e 195 

JRZ.e 194 

Label 26 

LD A,(BC) 57 

LD A,(DE) 57 

LDA.I 61 

LD A,(nn) 58 

LDA,R 62 

LD (BC),A 59 

LDD 96 

LDdd.(nn) 68 

LDdd.nn 65 

LD (DE),A 59 

LDDR 97 

LD (HL),n 54 

LD HL,(nn) 67 

LD (HL),r 52 

LDI 93 

LD l,A 62 

LDIR 94 

LD(IX + d),n 55 

LD(IX + d),r 52 

LD IX.nn 66 

LD IX,(nn) 69 

LD(IY + d),n 56 

LD(IY + d),r 53 

LD IY,nn 67 

LD IY,(nn) 70 

LD (nn),A 60 

LD (nn),dd 72 

LD(nn),HL 71 



Subject Page 

LD (nn),IX 73 

LD (nn),IY 74 

LD R,A 63 

LD r,(HL) 49 

LDr,(IX + d) 49 

LDr,(IY + d) 51 

LD r,n 48 

LD r,r* 47 

LDSP.HL 75 

LDSP.IX 76 

LDSP.IY 77 

Memory refresh register 248 

Mnemonics 26 

Model I — Subroutines 228 

NEG 133 

NOP 135 

Notations 4 

Numerical list of Z-80 instructions 234-239 

Object code 33 

Object code 4 

Object file 4 

Operands 26, 29 

Operations 27 

ORs 117 

OTDR 224 

OTIR 221 

OUT(C),r 219 

OUTD 223 

OUTI 220 

OUT(n),A 218 

Parity/Overflow flag 232 

POP IX 82 

POP IY 84 

POP qq 81 

Program counter 247 

Pseudo Operations 27-28 

PUSH IX 79 

PUSH IY 80 

PUSH qq 77 

Register configuration 246 

RESb.m 186 

RET 204 

RET cc 205 

RETI 207 

RETN 208 



254 



INDEX 



Subject Page 

RLA 152 

RLCA 151 

RLC(HL) 156 

RLC(IX + d) 157 

RLC(IY + d) 158 

RLC r 1 55 

RLD 173 

RLm 160 

RRA 154 

RRCA 153 

RRCm 162 

RRD 175 

RRm 164 

RST p 209 

Sample Programming 31-36 

SBCA.s 113 

SBCHL.ss 143 

SCF 135 

SETb.(HL) 182 

SETb,(IX + d) 183 

SETb,(IY + d) 185 

SETb.r 181 

Sign flag 233 

Using the TPSRC utility 227 

SLAm 166 

Source Code 4 

Source File 4 

Special keys 8,17 

Special Terms 4 

SRAm 169 

SRLm 171 

Stack Pointer 247 

Status flags 231 

SUBs 111 

Symbols 17 

Text 7 

Text buffer 7 

Text handling 7 

Text handling commands 9 

Trial Assembly 32 

XORs 119 

Z-80 instructions 37-226 

Zero flag 233 



255 















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